Volume 30 Issue 5
Sep.  2021
Turn off MathJax
Article Contents
SUN Shuang, LI Ming, ZHANG Baotong, LI Xiaokang, CAI Qifeng, LI Haixia, BI Ran, XU Xiaoyan, HUANG Ru. Analysis on Three-Dimensional Gate Edge Roughness of Gate-All-Around Devices[J]. Chinese Journal of Electronics, 2021, 30(5): 861-865. doi: 10.1049/cje.2021.06.008
Citation: SUN Shuang, LI Ming, ZHANG Baotong, LI Xiaokang, CAI Qifeng, LI Haixia, BI Ran, XU Xiaoyan, HUANG Ru. Analysis on Three-Dimensional Gate Edge Roughness of Gate-All-Around Devices[J]. Chinese Journal of Electronics, 2021, 30(5): 861-865. doi: 10.1049/cje.2021.06.008

Analysis on Three-Dimensional Gate Edge Roughness of Gate-All-Around Devices

doi: 10.1049/cje.2021.06.008
Funds:

This work is supported by the National Key Research and Development Plan (No.2016YFA0200504) and the National Natural Science Foundation of China (No.61927901).

  • Received Date: 2021-01-20
    Available Online: 2021-09-02
  • As the physical size of metal-oxide-semiconductor field effect transistor approaches the end of scaling down, the effect of process-induced variations such as gate edge roughness on device performance cannot be neglected. For gate-all-around devices, the three-dimensional gate profiles make the evaluation of gate edge roughness different and more complicated than that in planar metal-oxide-semiconductor field effect transistors. In this work, an evaluation algorithm was proposed to model the three-dimensional gate edge roughness in a real gate-all-around device. The results show that the typical trapezoidal gate is more likely to suffer from gate edge roughness effect than the ideal rectangular gate. The effect of the size of the gate and the correlation coefficient of the edges on the effective channel length variation was also studied.
  • loading
  • J. Guo, Z.N. Jian, W. Yan, et al., "Degradation and selfrecovery of polycrystalline silicon TFT CMOS inverters under NBTI stress", Chinese Journal of Electronics, Vol.28, No.4, pp.884-888, 2019.
    S.G. Huang, M. Lin, R.Y. Wang, et al., "A 400MHz singlechip CMOS transceiver for long range high definition video transmission in UAV application", Chinese Journal of Electronics, Vol.29, No.3, pp.554-562, 2020.
    J. He, F. Liu, W. Bian, et al., "A continuous analytic model for undoped (lightly doped) cylindrical surroundinggate MOSFETs by a carrier-based approach", Chinese Journal of Electronics, Vol.16, No.2, pp.239-242, 2007.
    Y. Zhao, S. Parke, F. Burke, et al., "Modeling of uniform/nonuniform doping effects for MOSFET based on BSIM", Chinese Journal of Electronics, Vol.13, No.3, pp.413-415, 2004.
    R. Huang, R.S.Wang, J. Zhuge, et al., "Characterization and analysis of Gate-all-around Si nanowire transistor for extreme scaling", 2011 IEEE Custom Integrated Circuits Conference, CICC 2011, San Jose, CA, USA, DOI:10.1109/CICC.2011.6055334, 2011
    M. Li, G. Chen, R. Huang, et al., "High performance GAA SNWT with a triangular cross section:Simulation and experiments", Applied Sciences Basel, Vol.8, No.9, pp.8-18, 2018.
    D. Nagy, G. Indalecio, L. Garcia, et al., "FinFET versus gate-all-around nanowire FET:Performance, scaling, and variability", IEEE Journal of the Electron Device Society, Vol.6, No.1, pp.332-340, 2018.
    X.L. Zhang, X.Y. Liu, L.X. Yin, et al., "Impacts of diameter and Ge content variation on the performance of Si1-xGex p-channel gate-all-around nanowire transistors", IEEE Transactions on Nanotechnology, Vol.17, No.1, pp.108-112, 2018.
    N. Zagni, F.M Puglisi, P. Pavan, et al., "Effects of mole fraction variations and scaling on total variability in InGaAs MOSFETs", Solid-State Electronics, Vol.159, pp.135-141, 2019.
    A. Sudarsanan, S. Venkateswarlu, K. Nayak, et al., "Impact of Fin line edge roughness and metal gate granularity on Variability of 10-nm Node SOI n-FinFET", IEEE Transactions on Electron Devices, Vol.66, No.11, pp.4646-4652, 2019.
    G. Espineira, D. Nagy, G. Indalecio, et al., "Impact of gate edge roughness variability on FinFET and gate-all-around nanowire FET", IEEE Transactions on Electron Devices, Vol.40, No.4, pp.510-513, 2019.
    Y.F. Wu, G.W. Bao, L.S. Dong, et al., "A study on three dimensional mask effect of attenuated phase-shift mask in advanced optical lithography", Chinese Journal of Electronics, Vol.29, No.4, pp.648-650, 2020.
    A. Rawat, N. Sharan, D.Y. Jiang, et al., "Experimental validation of process-induced variability aware spice simulation platform for Sub-20 nm FinFET technologies", IEEE Transactions on Electron Devices, Vol.68, No.3, pp.976-980, 2021.
    X.L. Li, X.Q. Yang, Z. Zhang, et al., "Impact of process fluctuations on reconfigurable silicon nanowire transistor", IEEE Transactions on Electron Devices, Vol.68, No.2, pp.885-891, 2021.
    N. Zagni, F.M Puglisi, P. Pavan, et al., "On the impact of channel compositional variations on total threshold voltage variability in nanoscale InGaAs MOSFETs", Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Granada, Spain, DOI:10.1109/ULIS.2018.8354745, 2018.
    Y.Q. Ren, L. Shen, K.L. Wang, et al., "The Influence of gate line edge roughness and thickness of silicon film on the performance of UTBB MOSFETs", IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp.509-511, 2018.
    Z. Zhang, X.B. Jiang, R.S. Wang, et al., "Extraction of process variation parameters in FinFET technology based on compact modeling and characterization", IEEE Transactions on Electron Devices, Vol.65, No.3, pp.847-854, 2018.
    C. Shin, "Variation-aware advanced CMOS devices and SRAM", Springer Series in Advanced Microelectronics, Vol.56, No.18, pp.19-35, 2016.
    N. Seoane, D. Nagy, G. Indalecio, et al., "A multimethod simulation toolbox to study performance and variability of nanowire FETs", Materials, Vol.12, No.15, DOI:10.3390/ma12152391, 2019.
    A. Rawat, A. Gorad and U. Ganguly, "Analytical estimation of LER-like variability in GAA nano-sheet transistors", International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), DOI:10.1109/VLSI-TSA.2019.8804637, 2019.
    S.R. Sriram and B. Bindu, "Study of line edge roughness induced threshold voltage fluctuations in double gate MOSFET", IEEE-India-Council International Conference (IEEE INDICON), DOI:10.1109/INDICON45594.2018.8987069, 2018.
    X.Q. Dong, M. Li, W.R. Zhang, et al., "Effective gate length model for asymmetrical gate-all-around silicon nanowire transistors", Science China Information Sciences, Vol.63, No.10, DOI:10.1007/s11432-019-2658-x, 2020.
    ]X.Q. Dong, Y.C. Yang, G. Chen, et al., "Impact of gate asymmetry on gate all around silicon nanowire transistor parasitic capacitance", IEEE International Conference on Solid State and Integrated Circuit Technology (ICSICT), Qindao, China, DOI:10.1109/ICSICT.2018.8565686, 2018.
  • 加载中

Catalog

    通讯作者: 陈斌, bchen63@163.com
    • 1. 

      沈阳化工大学材料科学与工程学院 沈阳 110142

    1. 本站搜索
    2. 百度学术搜索
    3. 万方数据库搜索
    4. CNKI搜索

    Article Metrics

    Article views (109) PDF downloads(16) Cited by()
    Proportional views
    Related

    /

    DownLoad:  Full-Size Img  PowerPoint
    Return
    Return