Volume 30 Issue 6
Nov.  2021
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LI Tiejun, MA Kefan, ZHANG Jianmin, “An Parallel FPGA SAT Solver Based on Multi-Thread and Pipeline,” Chinese Journal of Electronics, vol. 30, no. 6, pp. 1008-1016, 2021, doi: 10.1049/cje.2021.08.001
Citation: LI Tiejun, MA Kefan, ZHANG Jianmin, “An Parallel FPGA SAT Solver Based on Multi-Thread and Pipeline,” Chinese Journal of Electronics, vol. 30, no. 6, pp. 1008-1016, 2021, doi: 10.1049/cje.2021.08.001

An Parallel FPGA SAT Solver Based on Multi-Thread and Pipeline

doi: 10.1049/cje.2021.08.001

This work is supported by the National Key Research and Development Program of China (No.2018YFB0204301) and the National Natural Science Foundation of China (No.62072464, No.U19A2062).

  • Received Date: 2020-06-15
  • Rev Recd Date: 2021-07-02
  • Available Online: 2021-09-23
  • Publish Date: 2021-11-05
  • The Boolean Satisfiability (SAT) problem is the key problem in computer theory and application. A parallel multi-thread SAT solver named pprobSAT+ on a configurable hardware is proposed. In the algorithm, multithreads are executed simultaneously to hide the circuit stagnate. In order to improve the working frequency and throughput of the SAT solver, the deep pipeline strategy is adopted. When all data stored in block random access memory of the field programmable gate array, the solver can achieve maximum performance. If partial data are stored in the external memory, the size of the problem instances the SAT solver can be greatly improved. The experimental results show that the speedup of three-thread SAT solver is approximately 2.4 times with single thread, and shows that the pprobSAT+ have achieved substantial improvement while a solution is found.
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