Modeling and Measurement of 3D Solenoid Inductor Based on Through-Silicon Vias

Through-silicon via (TSV) provides vertical interconnectivity among the stacked dies in three-dimensional integrated circuits (3D ICs) and is a promising option to minimize 3D solenoid inductors for on-chip radio-frequency applications. In this paper, a rigorous analytical inductance model of 3D solenoid inductor is proposed based on the concept of loop and partial inductance. And a series of 3D samples are fabricated on 12-in high-resistivity silicon wafer using low-cost standard CMOS-compatible process. The results of the proposed model match very well with those obtained by simulation and measurement. With this model, the inductance can be estimated accurately and efficiently over a wide range of inductor windings, TSV height, space, and pitch.