Volume 32 Issue 2
Mar.  2023
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CUI Yuqiang, SHAN Weiwei, DAI Wentao, et al., “An Improved Path Delay Variability Model via Multi-Level Fan-Out-of-4 Metric for Wide-Voltage-Range Digital CMOS Circuits,” Chinese Journal of Electronics, vol. 32, no. 2, pp. 375-388, 2023, doi: 10.23919/cje.2021.00.447
Citation: CUI Yuqiang, SHAN Weiwei, DAI Wentao, et al., “An Improved Path Delay Variability Model via Multi-Level Fan-Out-of-4 Metric for Wide-Voltage-Range Digital CMOS Circuits,” Chinese Journal of Electronics, vol. 32, no. 2, pp. 375-388, 2023, doi: 10.23919/cje.2021.00.447

An Improved Path Delay Variability Model via Multi-Level Fan-Out-of-4 Metric for Wide-Voltage-Range Digital CMOS Circuits

doi: 10.23919/cje.2021.00.447
Funds:  This work was supported by the National Natural Science Foundation of China (62122021, 62074035) and the Natural Science Foundation of Jiangsu Province (BK20200002)
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  • Author Bio:

    Yuqiang CUI received the M.S. degree from South China Normal University, Guangzhou, China, in 2019. He is pursuing the Ph.D. degree in the School of Electronics and Engineering of Southeast University, Nanjing, China. His current research interests include the low power IC design, and adaptive circuits and systems. (Email: yq_cui@seu.edu.cn)

    Weiwei SHAN received the B.S. degree in microelectronics from Tianjin University, Tianjin, China, in 2003, and the Ph.D. degree in microelectronics from Tsinghua University, Beijing, China, in 2009. She is a Professor in National ASIC center at Southeast University, Nanjing, China. She was a Visiting Professor at Columbia University, New York, USA from 2018 to 2019. Her research mainly focuses on variation resilient adaptive VLSI circuits, ultralow power SoC design and countermeasure techniques of security circuits. She has published over 40 technical papers in conferences and journals, including ISSCC, JSSC, TCASI, TCASII, TCAD and so on, and authorized over 15 invention patents. (Email: wwshan@seu.edu.cn)

    Wentao DAI received the B.S. degrees in microelectronics from Yangzhou University, Yangzhou, China, in 2013, and the Ph.D. degree in electronics engineering from Southeast University, Nanjing, China, in 2019. His current research interests include the low power integrated circuit design, and adaptive circuits and systems

    Xinning LIU received the B.S., M.S., and Ph.D. degrees from Southeast University, Nanjing, China, in 2000, 2003, and 2015, respectively. He is currently a Lecturer with the School of Electronic Science and Engineering, Southeast University. His current research interests include low-power design technology and always-on circuits

    Jingjing GUO received the B.S. degree in microelectronics and M.S. degree in integrated circuit engineering from the Xidian University, Xi’an, China, in 2011 and 2014, respectively. She received the Ph.D. degree in microelectronics and solid state electronics from the Southeast University, Nanjing, China. She is currently a Lecturer with Nanjing University of Posts and Telecommunications, China. Her research interests include statistical timing analysis and low power circuit design

    Peng CAO received the B.S. and Ph.D. degrees in microelectronics from Southeast University, Nanjing, China, in 2002 and 2010, respectively. He is currently an Associate Professor with National ASIC System Engineering Research Center, Southeast University. His current research interests include reconfigurable computing and related VLSI designs. (Email: caopeng@seu.edu.cn)

  • Received Date: 2021-12-23
  • Accepted Date: 2022-06-21
  • Available Online: 2022-07-07
  • Publish Date: 2023-03-05
  • In advanced CMOS technology, process, voltage, and temperature (PVT) variations increase the paths’ latency in digital circuits, especially when operating at a low supply voltage. The fan-out-of-4 inverter chain (FO4 chain) metric has been proven to be a good metric to estimate the path’s delay variability, whereas the previous work ignored the non-independent characteristic between the adjacent cells in a path. In this study, an improved model of path delay variability is established to describe the relationship between the paths’ max-delay variability and an FO4 chain, which is based on multilevel FO4 metric and circuit-level parameters knobs (i.e., cell topology and driving strength) of the first few cells. We take the slew and load into account to improve the accuracy of this framework. Examples of 28 nm and 40 nm digital circuits show that our model conforms with Monte Carlo simulations as well as fabricated chips’ measurements. It is able to model the delay variability effectively to speed up the design process with limited accuracy loss. It also provides a deeper understanding and quick estimation of the path delay variability from the near-threshold to nominal voltages.
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  • [1]
    J. Keane, H. Eom, Tae-Hyoung Kim, et al., “Subthreshold logical effort: A systematic framework for optimal subthreshold device sizing,” in Proceedings of the 43rd Annual Design Automation Conference, New York, NY, USA, pp.425–428, 2006.
    [2]
    B. Liu, Z. Zhang, H. Cai, et al., “Self-compensation tensor multiplication unit for adaptive approximate computing in low-power CNN Processing,” Science China Information Sciences, vol.65, no.4, pp.149403–149403, 2022. doi: 10.1007/s11432-021-3242-6
    [3]
    W. Shan, W. Dai, L. Wan, et al., “A bi-directional, zero-latency adaptive clocking circuit in a 28-nm wide AVFS system,” IEEE Journal of Solid-State Circuits, vol.55, no.3, pp.826–836, 2020. doi: 10.1109/JSSC.2019.2959494
    [4]
    L. Fassio, L. Lin, R. De Rose, et al., “Trimming-less voltage reference for highly uncertain harvesting down to 0.25 V, 5.4 pW,” IEEE Journal of Solid-State Circuits, vol.56, no.10, pp.3134–3144, 2021. doi: 10.1109/JSSC.2021.3081440
    [5]
    H. Reyserhove and W. Dehaene, “Margin elimination through timing error detection in a near-threshold enabled 32-bit microcontroller in 40-nm CMOS,” IEEE Journal of Solid-State Circuits, vol.53, no.7, pp.2101–2113, 2018. doi: 10.1109/JSSC.2018.2821121
    [6]
    W. Shan, W. Dai, C. Zhang, et al., “TG-SPP: A one-transmission-gate short-path padding for wide-voltage-range resilient circuits in 28-nm CMOS,” IEEE Journal of Solid-State Circuits, vol.55, no.5, pp.1422–1436, 2020. doi: 10.1109/JSSC.2019.2948164
    [7]
    W. Shan, X. Shang, X. Wan, et al., “A wide-voltage-range half-path timing error-detection system with a 9-transistor transition-detector in 40-nm CMOS,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol.66, no.6, pp.2288–2297, 2019. doi: 10.1109/TCSI.2019.2893294
    [8]
    P. Luo, D. Wang, and X. Peng, “An adaptive voltage scaling buck converter with preset circuit,” Chinese Journal of Electronics, vol.28, no.2, pp.229–236, 2019. doi: 10.1049/cje.2019.01.007
    [9]
    X. Shang, W. Shan, Y. Xiang, et al., “Low overhead and fast reaction adaptive clocking system for voltage droop tolerance,” Chinese Journal of Electronics, vol.28, no.3, pp.503–507, 2019. doi: 10.1049/cje.2019.02.009
    [10]
    J. Li, X. Wan, J. Wu, et al., “Cache power optimization based on compare-based adaptive clock gating and its 65nm SoC implementation,” Chinese Journal of Electronics, vol.26, no.1, pp.128–131, 2017. doi: 10.1049/cje.2016.06.029
    [11]
    J. P. Kulkarni, C. Tokunaga, P. A. Aseron, et al., “A 409 GOPS/W adaptive and resilient domino register file in 22 nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging,” IEEE Journal of Solid-State Circuits, vol.51, no.1, pp.117–129, 2016. doi: 10.1109/JSSC.2015.2463083
    [12]
    Z. Li, T. Zhu, Z. Chen, et al., “Eliminating timing errors through collaborative design to maximize the throughput,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol.25, no.2, pp.670–682, 2017. doi: 10.1109/TVLSI.2016.2587810
    [13]
    Z. Chen, H. Wang, G. Xie, et al., “A comprehensive stochastic design methodology for hold-timing resiliency in voltage-scalable design,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.26, no.10, pp.2118–2131, 2018. doi: 10.1109/TVLSI.2018.2847622
    [14]
    S. Keller, D. M. Harris, A. J. Martin, et al., “A compact transregional model for digital CMOS circuits operating near threshold,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol.22, no.10, pp.2041–2053, 2014. doi: 10.1109/TVLSI.2013.2282316
    [15]
    V. M. van Santen, J. Martin-Martinez, H. Amrouch, et al., “Reliability in super- and near-threshold computing: A unified model of RTN, BTI, and PV,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol.65, no.1, pp.293–306, 2018. doi: 10.1109/TCSI.2017.2717790
    [16]
    H. Jooypa and D. Dideban, “Impact analysis of statistical variability on the accuracy of a propagation delay time compact model in nano-CMOS technology,” Journal of Computational Electronics, vol.17, no.1, pp.192–204, 2018. doi: 10.1007/s10825-017-1108-2
    [17]
    H. Jooypa and D. Dideban, “Statistical strategies to reproduce the propagation delay time variability using compact models,” IEEE Transactions on Circuits and Systems Ⅱ: Express Briefs, vol.66, no.11, pp.1880–1884, 2019. doi: 10.1109/TCSII.2019.2895364
    [18]
    K. Papachatzopoulos and V. Paliouras, “Static delay variation models for ripple-carry and borrow-save adders,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol.66, no.7, pp.2546–2559, 2019. doi: 10.1109/TCSI.2019.2900151
    [19]
    C. Lin, W. He, Y. Sun, et al., “MEDAC: A metastability condition detection and correction technique for a near-threshold-voltage multi-voltage-/frequency-domain network-on-chip,” IEEE Journal of Solid-State Circuits, vol.56, no.7, pp.2270–2280, 2021. doi: 10.1109/JSSC.2020.3036856
    [20]
    W. Shan, Y. Cui, W. Dai, X. Liu, et al., “An efficient path delay variability model for wide-voltage-range digital circuits,” Science China Information Sciences, vol.66, no.2, pp.129401–129401, 2023. doi: 10.1007/s11432-021-3407-2
    [21]
    Y. Han, B. Han, Z. Hu, et al., “Prediction and variation of the auroral oval boundary based on a deep learning model and space physical parameters,” Nonlinear Processes in Geophysics, vol.27, no.1, pp.11–22, 2020. doi: 10.5194/npg-27-11-2020
    [22]
    P. Cao, J. Wu, Z. Liu, et al., “A statistical current and delay model based on log-skew-normal distribution for low voltage region,” in Proc. of the 2019 Great Lakes Symposium on VLSI, New York, NY, USA, pp.323–326, 2019.
    [23]
    Z. Wu, P. Maurine, N. Azemard, et al., “Delay-correlation-aware SSTA based on conditional moments,” Microelectronics Journal, vol.43, no.4, pp.263–273, 2012. doi: 10.1016/j.mejo.2012.01.003
    [24]
    J. Guo, J. Zhu, M. Wang, et al., “Analytical inverter chain’s delay and its variation model for sub-threshold circuits,” IEICE Electronics Express, vol.14, no.11, article no.20170390, 2017.
    [25]
    A. Moshrefi, H. Aghababa, O. Shoaei, et al., “Statistical estimation of delay in nano-scale CMOS circuits using Burr distribution,” Microelectronics Journal, vol.79, pp.30–37, 2018. doi: 10.1016/j.mejo.2018.06.013
    [26]
    R. Rithe, S. Chou, J. Gu, et al., “The effect of random dopant fluctuations on logic timing at low voltage,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.20, no.5, pp.911–924, 2012. doi: 10.1109/TVLSI.2011.2124477
    [27]
    A. B. Kahng, “New game, new goal posts: A recent history of timing closure,” in Proc. of the 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, pp.1–6, 2015.
    [28]
    W. F. Lu and L. L. Sun, “Compact modeling of response time and random-dopant-fluctuation-induced variability in nanoscale CMOS inverter,” Microelectronics Journal, vol.45, no.6, pp.678–682, 2014. doi: 10.1016/j.mejo.2014.03.019
    [29]
    V. Veetil, K. Chopra, D. Blaauw, et al., “Fast statistical static timing analysis using smart Monte Carlo techniques,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol.30, no.6, pp.852–865, 2011. doi: 10.1109/TCAD.2011.2108030
    [30]
    M. Alioto, G. Palumbo, M. Pennisi, “Understanding the effect of process variations on the delay of static and domino logic,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.18, no.5, pp.697–710, 2010. doi: 10.1109/TVLSI.2009.2015455
    [31]
    S. Saurabh, H. Shah, and S. Singh, “Timing closure problem: Review of challenges at advanced process nodes and solutions,” IETE Technical Review, vol.36, no.6, pp.580–593, 2019. doi: 10.1080/02564602.2018.1531733
    [32]
    H. Reyserhove and W. Dehaene, Efficient Design of Variation-Resilient Ultra-Low Energy Digital Processors, Springer, Seattle, WA, USA, pp.53–85, 2019.
    [33]
    I. Tsiokanos, L. Mukhanov, D. S. Nikolopoulos, et al., “Variation-aware pipelined cores through path shaping and dynamic cycle adjustment: Case study on a floating-point unit,” in Proceedings of the International Symposium on Low Power Electronics and Design, New York, NY, USA, pp.1–6, 2018.
    [34]
    W. Hoeffding and H. Robbins, “The central limit theorem for dependent random variables,” Duke Mathematical Journal, vol.15, no.3, pp.773–780, 1948.
    [35]
    C. Y. Chuang and W. K. Mak, “Accurate closed-form parameterized block-based statistical timing analysis applying skew-normal distribution,” in Proc. of the 10th International Symposium on Quality Electronic Design, San Jose, CA, USA, pp.68–73, 2009.
    [36]
    M. Merrett and M. Zwolinski, “Monte Carlo static timing analysis with statistical sampling,” Microelectronics Reliability, vol.54, no.2, pp.464–474, 2014. doi: 10.1016/j.microrel.2013.10.016
    [37]
    X. Zhou, F. Yang, H. Zhou, et al., “Efficient statistical timing analysis for circuits with post-silicon tunable buffers,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol.97, no.11, pp.2227–2235, 2014.
    [38]
    S. Ramprasath, M. Vijaykumar, and V. Vasudevan, “A skew-normal canonical model for statistical static timing analysis,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.24, no.6, pp.2359–2368, 2015.
    [39]
    L. Cheng, F. Gong, W. Xu, et al., “Fourier series approximation for max operation in non-Gaussian and quadratic statistical static timing analysis,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.20, no.8, pp.1383–1391, 2011.
    [40]
    A. A. Bayrakci, A. Demir, and S. Tasiran, “Fast Monte Carlo estimation of timing yield with importance sampling and transistor-level circuit simulation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.29, no.9, pp.1328–1341, 2010. doi: 10.1109/TCAD.2010.2049042
    [41]
    A. Mutlu, J. Le, and R. Molina, “A parametric approach for handling local variation effects in timing analysis,” in Proc. of the 46th Annual Design Automation Conference, San Francisco, CA, USA pp.126–129, 2009.
    [42]
    Y. Zhang and B. Calhoun, “Fast, accurate variation-aware path timing computation for sub-threshold circuits,” in Proc. of the Fifteenth International Symposium on Quality Electronic Design, Santa Clara, CA, USA, pp.243–248, 2014.
    [43]
    M. Alioto, G. Scotti, and A. Trifiletti, “A novel framework to estimate the path delay variability on the back of an envelope via the fan-out-of-4 metric,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol.64, no.8, pp.2073–2085, 2017. doi: 10.1109/TCSI.2017.2687059
    [44]
    B. Lasbouygues, S. Engels, R. Wilson, et al., “Logical effort model extension to propagation delay representation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.25, no.9, pp.1677–1684, 2006. doi: 10.1109/TCAD.2005.857400
    [45]
    J. M. Yoon, H. Do, D. Koh, et al., “A capacitor-coupled offset-canceled sense amplifier for DRAMs with reduced variation of decision threshold voltage,” IEEE Journal of Solid-State Circuits, vol.55, no.8, pp.2219–2227, 2020. doi: 10.1109/JSSC.2020.2972545
    [46]
    A. K. Mal and A. S. Dhar, “Modified Elmore delay model for VLSI interconnect,” in Proceedings of the 53rd IEEE International Midwest Symposium on Circuits and Systems, Seattle, WA, USA, pp.793–796, 2010.
    [47]
    A. Morgenshtein, E. G. Friedman, R. Ginosar, et al., “Unified logical effort-a method for delay evaluation and minimization in logic paths with RC interconnect,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.18, no.5, pp.689–696, 2009.
    [48]
    X. Yuan, P. Owczarczyk, A. J. Drake, et al., “Design considerations for reconfigurable delay circuit to emulate system critical paths,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.23, no.11, pp.2714–2718, 2014.
    [49]
    M. Alioto, G. Scotti, and A. Trifiletti, “Design-oriented models for quick estimation of path delay variability via the fan-out-of-4 metric,” in Proceedings of 2017 IEEE International Symposium on Circuits and Systems, Baltimore, MA, USA, pp.1–4, 2017.
    [50]
    H. Kwon, J. H. Kim, S. Kang, et al., “SoftCorner: Relaxation of corner values for deterministic static timing analysis of VLSI systems,” IEEE Access, vol.6, pp.60115–60127, 2018. doi: 10.1109/ACCESS.2018.2875474
    [51]
    G. Sannena and B. P. Das, “Low overhead warning flip-flop based on charge sharing for timing slack monitoring,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.26, no.7, pp.1223–1232, 2018. doi: 10.1109/TVLSI.2018.2810954
    [52]
    P. J. Bickel and E. Levina, “Covariance regularization by thresholding,” The Annals of Statistics, vol.36, no.6, pp.2577–2604, 2008.
    [53]
    W. G. Cochran, “Analysis of covariance: Its nature and uses,” Biometrics, vol.13, no.3, pp.261–281, 1957. doi: 10.2307/2527916
    [54]
    W. Dai, W. Shan, X. Shang, et al., “HTD: A light-weight holosymmetrical transition detector for wide-voltage-range variation resilient ICs,” IEEE Trans. on Circuits and Systems I: Regular Papers, vol.65, no.11, pp.3907–3917, 2018. doi: 10.1109/TCSI.2018.2857836
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