Volume 32 Issue 2
Mar.  2023
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CUI Yuqiang, SHAN Weiwei, DAI Wentao, et al., “An Improved Path Delay Variability Model via Multi-Level Fan-Out-of-4 Metric for Wide-Voltage-Range Digital CMOS Circuits,” Chinese Journal of Electronics, vol. 32, no. 2, pp. 375-388, 2023, doi: 10.23919/cje.2021.00.447
Citation: CUI Yuqiang, SHAN Weiwei, DAI Wentao, et al., “An Improved Path Delay Variability Model via Multi-Level Fan-Out-of-4 Metric for Wide-Voltage-Range Digital CMOS Circuits,” Chinese Journal of Electronics, vol. 32, no. 2, pp. 375-388, 2023, doi: 10.23919/cje.2021.00.447

An Improved Path Delay Variability Model via Multi-Level Fan-Out-of-4 Metric for Wide-Voltage-Range Digital CMOS Circuits

doi: 10.23919/cje.2021.00.447
Funds:  This work was supported by the National Natural Science Foundation of China (62122021, 62074035) and the Natural Science Foundation of Jiangsu Province (BK20200002)
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  • Author Bio:

    Yuqiang CUI received the M.S. degree from South China Normal University, Guangzhou, China, in 2019. He is pursuing the Ph.D. degree in the School of Electronics and Engineering of Southeast University, Nanjing, China. His current research interests include the low power IC design, and adaptive circuits and systems. (Email: yq_cui@seu.edu.cn)

    Weiwei SHAN received the B.S. degree in microelectronics from Tianjin University, Tianjin, China, in 2003, and the Ph.D. degree in microelectronics from Tsinghua University, Beijing, China, in 2009. She is a Professor in National ASIC center at Southeast University, Nanjing, China. She was a Visiting Professor at Columbia University, New York, USA from 2018 to 2019. Her research mainly focuses on variation resilient adaptive VLSI circuits, ultralow power SoC design and countermeasure techniques of security circuits. She has published over 40 technical papers in conferences and journals, including ISSCC, JSSC, TCASI, TCASII, TCAD and so on, and authorized over 15 invention patents. (Email: wwshan@seu.edu.cn)

    Wentao DAI received the B.S. degrees in microelectronics from Yangzhou University, Yangzhou, China, in 2013, and the Ph.D. degree in electronics engineering from Southeast University, Nanjing, China, in 2019. His current research interests include the low power integrated circuit design, and adaptive circuits and systems

    Xinning LIU received the B.S., M.S., and Ph.D. degrees from Southeast University, Nanjing, China, in 2000, 2003, and 2015, respectively. He is currently a Lecturer with the School of Electronic Science and Engineering, Southeast University. His current research interests include low-power design technology and always-on circuits

    Jingjing GUO received the B.S. degree in microelectronics and M.S. degree in integrated circuit engineering from the Xidian University, Xi’an, China, in 2011 and 2014, respectively. She received the Ph.D. degree in microelectronics and solid state electronics from the Southeast University, Nanjing, China. She is currently a Lecturer with Nanjing University of Posts and Telecommunications, China. Her research interests include statistical timing analysis and low power circuit design

    Peng CAO received the B.S. and Ph.D. degrees in microelectronics from Southeast University, Nanjing, China, in 2002 and 2010, respectively. He is currently an Associate Professor with National ASIC System Engineering Research Center, Southeast University. His current research interests include reconfigurable computing and related VLSI designs. (Email: caopeng@seu.edu.cn)

  • Received Date: 2021-12-23
  • Accepted Date: 2022-06-21
  • Available Online: 2022-07-07
  • Publish Date: 2023-03-05
  • In advanced CMOS technology, process, voltage, and temperature (PVT) variations increase the paths’ latency in digital circuits, especially when operating at a low supply voltage. The fan-out-of-4 inverter chain (FO4 chain) metric has been proven to be a good metric to estimate the path’s delay variability, whereas the previous work ignored the non-independent characteristic between the adjacent cells in a path. In this study, an improved model of path delay variability is established to describe the relationship between the paths’ max-delay variability and an FO4 chain, which is based on multilevel FO4 metric and circuit-level parameters knobs (i.e., cell topology and driving strength) of the first few cells. We take the slew and load into account to improve the accuracy of this framework. Examples of 28 nm and 40 nm digital circuits show that our model conforms with Monte Carlo simulations as well as fabricated chips’ measurements. It is able to model the delay variability effectively to speed up the design process with limited accuracy loss. It also provides a deeper understanding and quick estimation of the path delay variability from the near-threshold to nominal voltages.
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