Volume 33 Issue 2
Mar.  2024
Turn off MathJax
Article Contents
Peijie LI, Jianliang SHEN, Ping LYU, et al., “Architecture Design of Protocol Controller Based on Traffic-Driven Software Defined Interconnection,” Chinese Journal of Electronics, vol. 33, no. 2, pp. 362–370, 2024 doi: 10.23919/cje.2022.00.094
Citation: Peijie LI, Jianliang SHEN, Ping LYU, et al., “Architecture Design of Protocol Controller Based on Traffic-Driven Software Defined Interconnection,” Chinese Journal of Electronics, vol. 33, no. 2, pp. 362–370, 2024 doi: 10.23919/cje.2022.00.094

Architecture Design of Protocol Controller Based on Traffic-Driven Software Defined Interconnection

doi: 10.23919/cje.2022.00.094
More Information
  • Author Bio:

    Peijie LI received the M.S. degree in communication engineering from Information Engineering University in 2014. Since September 2014, he has been working as a Research Assistant at the Institute of Information Technology in Information Engineering University. He is currently working towards the Ph.D. degree in Information Engineering University. His research interests include software defined hardware, SerDes, and System on Wafer. (Email: lpj@ndsc.com.cn)

    Jianliang SHEN received the Ph.D degree in National University of Defense Technology. He is currently an Associate Professor of Information Engineering University. His research interests include software defined interconnection, system architecture design and SoC technology. (Email: sjl@ndsc.com.cn)

    Ping LYU received the Ph.D degree in communication engineering from Information Engineering University in 2019. Currently, she is a Professor and M.S. supervisor. Her research interests include new generation network information system architecture, and she is engaged in Large scale integrated circuit design. (Email: lp@ndsc.com.cn)

    Chunlei DONG received the M.S. degree in microelectronics from University of Chinese Academy of Sciences in 2014. Since September 2014, he has been working as a Research Assistant at the Institute of Information Technology in Information Engineering University. His research interests include software defined Interconnection, switching fabric, and system on wafer. (Email: dcl@ndsc.com.cn)

    Ting CHEN received the B.S. degree in microelectronics from University of Electronic and Scientific Technology of China in 2008, M.S. and Ph.D degrees in electrical science and technology from the National University of Defense Technology, China, in 2010 and 2014, respectively. He is currently working as a Research Assistant at the Institute of Information Technology in Information Engineering University. His research interests include high performance interconnection structure, parallel processing architectures, and circuits. (Email: ct@ndsc.com.cn)

  • Corresponding author: Email: lpj@ndsc.com.cn
  • Received Date: 2022-04-19
  • Accepted Date: 2023-03-21
  • Available Online: 2023-07-05
  • Publish Date: 2024-03-05
  • To solve the problems of redundant logic resources and poor scalability in protocol controller circuits among communication networks, we propose a traffic-driven software defined interconnection (TSDI) mechanism. The unified software defined interconnection interface standards and the normalized interconnection topology are designed to implement the architecture of TSDI-based protocol controller. The key indicators of power, performance and area (PPA) can be realized while resolving the flexible interconnection of the controller. We designed a TSDI-based RapidIO controller as an example. Compared to traditional designs, the design could achieve more protocol scalability, and RapidIO protocol standards of Gen4 could be supported directly. The key PPA indicators, such as a lower delay of 56.1 ns and more than twice throughput of 98.1 Gbps, were achieved at the cost of a 23.4% area increase.
  • loading
  • [1]
    P. Lv, Q. R. Liu, J. X. Wu, et al., “New generation software-defined architecture,” Scientia Sinica Informationis, vol. 48, no. 3, pp. 315–328, 2018. (in Chinese) doi: 10.1360/N112017-00204
    [2]
    J. X. Wu, “Thoughts on the development of novel network technology,” Science China Information Sciences, vol. 61, no. 10, article no. 101301, 2018. doi: 10.1007/s11432-018-9456-x
    [3]
    X. T. Guo, Y. W. Lei, and Y. Guo, “Design and implementation of dual-channel serial RapidIO for multiple transmission modes,” Computer Engineering & Science, vol. 41, no. 2, pp. 233–239, 2019. (in Chinese) doi: 10.3969/j.issn.1007-130X.2019.02.006
    [4]
    C. F. Dan, J. Li, S. L. Jing, et al., “Design of RapidIO bus system based on software configuration,” Microcontrollers & Embedded Systems, vol. 20, no. 7, pp. 11–14, 2020. (in Chinese)
    [5]
    J. C. Shen, “Design of DMA high-speed transmission scheme based on general RapidIO controller,” Microcontrollers & Embedded Systems, vol. 20, no. 7, pp. 20–24, 2020. (in Chinese)
    [6]
    Xilinx, “Serial RapidIO endpoint LogiCORE IP product guide 7,” Xilinx, 2017.
    [7]
    Mobiveil, “Mobiveil RapidIO controller (GRIO),” Mobiveil, 2016.
    [8]
    IDT, “RapidIO-IP-10xN user manual,” IDT, 2017.
    [9]
    M. Cicioğlu and A. Çalhan, “A multiprotocol controller deployment in SDN-based IoMT architecture,” IEEE Internet of Things Journal, vol. 9, no. 21, pp. 20833–20840, 2022. doi: 10.1109/JIOT.2022.3175669
    [10]
    E. Hrynkiewicz and M. Chmiel, “Programmable logic controller-basic structure and idea of programming,” Electrical Review, vol. 88, no. 11b, pp. 98–101, 2012.
    [11]
    E. A. Suvorova and V. V. Rozanov, “Dynamic reconfigurable packet distribution unit for embedded systems,” in 2019 Wave Electronics and its Application in Information and Telecommunication Systems (WECONF), St. Petersburg, Russia, pp.1–9, 2019.
    [12]
    E. Suvorova, “An approach to dynamic reconfigurable transport protocol controller unit development,” in 2020 26th Conference of Open Innovations Association (FRUCT), Yaroslavl, Russia, pp.429–437, 2020.
    [13]
    A. Karatkevich, A. Bukowiec, M. Doligalski, et al., Design of Reconfigurable Logic Controllers. Springer, Cham, Switzerland, 2016, doi: 10.1007/978-3-319-26725-8.
    [14]
    M. Tsavos, N. Sklavos, and G. P. Alexiou, “Lightweight security data streaming, based on reconfigurable logic, for FPGA platform,” in 2020 23rd Euromicro Conference on Digital System Design (DSD), Kranj, Slovenia, pp.277–280, 2020.
    [15]
    S. Xydis, G. Economakos, D. Soudris, et al., “High performance and area efficient flexible DSP datapath synthesis,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 3, pp. 429–442, 2011. doi: 10.1109/TVLSI.2009.2034167
    [16]
    S. Xydis, G. Palermo, and C. Silvano, “Thermal-aware datapath merging for coarse-grained reconfigurable processors,” in 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, pp.1649–1654, 2013.
    [17]
    E. A. Suvorova, “An approach for development of RISC- V based transport layer controller,” in 2021 Wave Electronics and its Application in Information and Telecommunication Systems (WECONF), St. Petersburg, Russia, pp.1–9, 2021.
    [18]
    P. D. Schiavone, D. Rossi, A. Di Mauro, et al., “Arnold: An eFPGA-augmented RISC-V SoC for flexible and low-power IoT end nodes,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 4, pp. 677–690, 2021. doi: 10.1109/TVLSI.2021.3058162
    [19]
    P. Lv, Q. R. Liu, H. C. Chen, et al., “Domain-oriented software defined computing architecture,” China Communications, vol. 16, no. 6, pp. 162–172, 2019. doi: 10.23919/JCC.2019.06.013
  • 加载中

Catalog

    通讯作者: 陈斌, bchen63@163.com
    • 1. 

      沈阳化工大学材料科学与工程学院 沈阳 110142

    1. 本站搜索
    2. 百度学术搜索
    3. 万方数据库搜索
    4. CNKI搜索

    Figures(13)  / Tables(3)

    Article Metrics

    Article views (602) PDF downloads(20) Cited by()
    Proportional views
    Related

    /

    DownLoad:  Full-Size Img  PowerPoint
    Return
    Return