SiC Double Trench MOSFET with Split Gate and Integrated Schottky Barrier Diode for Ultra-low Power Loss and Improved Short-Circuit Capability

ZHANG Jinping; WU Qinglin; CHEN Zixun; ZOU Hua; ZHANG Bo

doi:10.23919/cje.2022.00.394

Volume 33 Issue 5

Sep. 2024

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Article Navigation > Chinese Journal of Electronics > 2024 > 33(5): 1127-1136

Jinping ZHANG, Qinglin WU, Zixun CHEN, et al., “SiC Double Trench MOSFET with Split Gate and Integrated Schottky Barrier Diode for Ultra-low Power Loss and Improved Short-Circuit Capability,” Chinese Journal of Electronics, vol. 33, no. 5, pp. 1127–1136, 2024 doi: 10.23919/cje.2022.00.394

Citation:

Jinping ZHANG, Qinglin WU, Zixun CHEN, et al., “SiC Double Trench MOSFET with Split Gate and Integrated Schottky Barrier Diode for Ultra-low Power Loss and Improved Short-Circuit Capability,” Chinese Journal of Electronics, vol. 33, no. 5, pp. 1127–1136, 2024 doi: 10.23919/cje.2022.00.394

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SiC Double Trench MOSFET with Split Gate and Integrated Schottky Barrier Diode for Ultra-low Power Loss and Improved Short-Circuit Capability

doi: 10.23919/cje.2022.00.394

1.
State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China

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Author Bio:
Jinping ZHANG received the Ph.D. degree from University of Electronic Science and Technology of China (UESTC), Chengdu, China, in 2009. He is currently a Professor with UESTC. His research interests include semiconductor power devices and integrated circuits. (Email: jinpingzhang@uestc.edu.cn)

Qinglin WU received the B.E. degree from Nanjing University of Information Science and Technology, Nanjing, China, in 2020. He is currently pursuing the M.S. degree at University of Electronic Science and Technology of China, Chengdu, China. His research interest focuses on semiconductor power devices. (Email:912206404@qq.com)

Zixun CHEN is currently pursuing the Ph.D. degree from University of Electronic Science and Technology of China, Chengdu, China. His current research interests include the structure, process and reliability of semiconductor power devices and their applications. (Email: 1062403879@qq.com)

Hua ZOU received the M.S. degree from University of Electronic Science and Technology of China, Chengdu, China, in 2019. His research interest focuses on semiconductor power devices. (Email: 254024405@qq.com)

Bo ZHANG received the B.S. degree in electronic engineering from Beijing Institute of Technology, Beijing, China, in 1985 and M.S. degree in electronic engineering from UESTC, Chengdu, China, in 1988. He is currently a Professor with UESTC, where he is also the Director of the Center for the Integrated Circuits. He has authored or coauthored over 300 referred journal papers and a number of books/book chapters. He has held key positions in and has served on various international conferences committees. In particular, he was the TPC member of the International Symposium on Power Semiconductor Devices and ICs from 2010 to 2015. He is also the Editor of IEEE Transactions on Electron Devices. (Email: bozhang@uestc.edu.cn)
Corresponding author: Email: jinpingzhang@uestc.edu.cn
Received Date: 2022-11-18
Accepted Date: 2023-03-21

Available Online: 2023-07-15

Publish Date: 2024-09-05

Abstract

Abstract

A silicon carbide (SiC) double trench metal-oxide-semiconductor field effect transistor (DTMOS) with split gate (SG) and integrated Schottky barrier diode (SBD) is proposed for the first time. The proposed device features two enhanced deep trenches in the surface, in which a source-connected SG with a thicker dielectric layer is located at the bottom of the deep gate trench and an integrated SBD is located at the sidewall of the deep source trench (DST). Combined with shielding effect provided by the P⁺ shield layer under the DST and integrated SBD, the proposed structure not only reduces the reverse transfer capacitance ($C _{\rm rss}$) and gate-drain charge ($ {Q} _{\rm gd} $) but also restrains the saturation drain current ($ {I} _{\rm d, sat} $) and improves the diode performance of the device. Numerical analysis results show that compared with the Con-DTMOS and Con-DTMOS with external SBD diode, the turn-on loss ($ {E} _{\rm on} $) and turn-off loss ($ {E} _{\rm off} $) for the proposed device are reduced by 56.4%/70.4% and 56.6%/69.9%, respectively. Moreover, the $ {I} _{\rm d, sat} $ at the $ {V} _{\rm gs} $ of 18 V for the proposed device is reduced by 74.4% and the short-circuit withstand time ($ {t} _{\rm SC} $) is improved by about 7.5 times. As a result, an ultra-low power loss and improved short-circuit capability is obtained for the proposed device.

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References(26)

References

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