Figure
1.
The overall structure of super-large array CIS.
| Citation: |
Ruiming XU, Zhongjie GUO, Suiyang LIU, et al., “Global Ramp Uniformity Correction Method for Super-Large Array CMOS Image Sensors,” Chinese Journal of Electronics, vol. 33, no. 2, pp. 415–422, 2024. DOI: 10.23919/cje.2022.00.397
|
XU Ruiming: Ruiming XU is pursuing the M.S. degree in Xi’an University of Technology. His current research interests include high performance mixed signal integration circuit design. (Email: rmxu@stu.xaut.edu.cn)
GUO Zhongjie: Zhongjie GUO received the B.S. and M.S. degrees from Xidian University, China, in 2004 and 2007, respectively, and Ph.D. degree in microelectronics engineering from Xi’an Microelectronic Technology Institute, China, in 2012. His current research interests include high performance mixed signal integration circuit design. (Email: zjguo@xaut.edu.cn)
LIU Suiyang: Suiyang LIU was born in Xi’an, Shaanxi Province, China, in 1997. She received the B.S. degree in integrated circuit design and integrated systems from Xi’an University of Technology in 2019 and the M.S. degree in electronic science and technology from Xi’an University of Technology in 2022. Her research interests include organic photodetectors, TSV, and CMOS image sensors. (Email: 1220310003@stu.xaut.edu.cn)
YU Ningmei: Ningmei YU received the B.S. degree in electronic engineering from the Xi’an University of Technology, Xi’an, China, in 1986, and the M.S. and Ph.D. degrees in electronic engineering from Tohoku University, Sendai, Japan, in 1996 and 1999, respectively. She is currently a Professor with the Department of Electric Engineering, Xi’an University of Technology. Her current research interests include very large scale integration circuit design. (Email: yunm@xaut.edu.cn)
In recent years, CMOS image sensors (CISs) have been widely used in digital single-lens reflex (DSLR) cameras, aerospace, medical equipment and other fields [1], [2]. With the advent of the era of big data, people have put forward higher requirements for the resolution, frame rate and integration of CIS. In order to improve the resolution, CISs need to increase the number of pixels and chip size. In this case, the length of metal transmission lines used to transmit global signals has exceeded 100 mm. Parasitic effects will increase significantly, which will seriously affect the signal transmission quality. In CIS, the ramp signal is typically used as a global signal to drive all column-level analog to digital converters (ADCs). The accuracy of the ramp signal directly affects the conversion accuracy of the column-level ADC. However, in the super-large array CISs, the parasitic effect of the metal transmission line will cause the input ramp signal to each column-level ADC to be different, which will affect the conversion result of the column-level ADC and generate column fixed-pattern noise (FPN). Column FPN has a greater impact on image quality than other types of FPN [3]. In order not to affect the imaging quality of the CIS, the ramp non-uniformity error needs to be controlled within 1/2 LSB. At present, the mainstream ramp generating circuit structures used by CIS include integral ramp generating circuit [4], [5], resistive ramp generating circuit [6], capacitive ramp generating circuit [7], [8], and current steering ramp generating circuit [9], [10]. In [11], an integral ramp generation circuit is used to reduce the gain error of the ramp signal. However, when it is used in super-large array CIS, the ramp non-uniformity error still exists. In [12], the current steering ramp generating circuit is used. When it is used in super-large array CIS, due to the parasitic effect of the metal transmission line, it is necessary to allow sufficient settling time for each voltage switching to ensure the resolution of the ramp signal. At 12-bit resolution, the ramp time is at least 100 μs, which will greatly limit the frame rate of CIS. At present, the main techniques to eliminate column FPN are digital correlation double sampling (DCDS), dynamic column switching (DCS), and gray value compensation [13]-[15]. DCS and gray value compensation technology can only eliminate column FPN that obey random distribution, while the column FPN introduced by ramp non-uniformity error is fixed error for each column. DCDS will introduce additional time consumption and limit the frame rate improvement of CIS. Especially for large array CIS, DCDS will lead to a sharp increase in the total readout time.
In order to eliminate the ramp non-uniformity error of the super-large array CIS, this paper proposes a ramp uniformity correction method based on the error storage and level shifting technology without affecting the accuracy of the ramp signal and the frame rate of the CIS, which effectively reduces the ramp non-uniformity error.
The remainder of this paper is organized as follows. Section II describes the structural characteristics of CIS. In Section III, ramp non-uniformity errors are analyzed. Section IV describes the ramp uniformity correction method. Section V contains the simulation results. Finally, the conclusions are drawn in Section VI.
As shown in Figure 1, the overall architecture of the super-large array CIS includes modules such as pixel array, column-level readout circuit and ramp generation circuit [16]. To simplify the design of column-level readout circuits and improve reliability, single-slope analog-to-digital converters (SS ADCs) are often used [17]-[19]. In CIS, the ramp signal typically drives all column-level ADCs as a global signal [20]-[25].
In this case, the length of the metal transmission line used to transmit the ramp signal is related to the number of pixels and the size of the pixel. The specific relationship is shown in (1).
|
L=H×S |
(1) |
where L is the length of the metal transmission line, H is the number of horizontal columns of the pixel array, and S is the size of a single pixel. According to the structural characteristics of the column-level SS ADC, the ramp generation circuit used in this paper is an integral ramp generation circuit. VRAMP can be described by
|
VRAMP=VCM+IREF×tC |
(2) |
where VCM is the starting operating voltage of the ramp signal, IREF is the integral current, C is the integral capacitor, and t is the integral time. To simplify the analysis, a distributed RC model is used to simulate parasitic effects on metal transmission lines. As shown in Figure 2, the parasitic model of the metal transmission line is built in this paper, where RP is the equivalent parasitic resistance, CP is the equivalent parasitic capacitance, and CL is the load capacitance. In the parasitic model of the metal transmission line, when the ramp signal (VRAMP) drives all capacitors from the left input, the voltage at each node is
|
VRAMP(n)=VRAMP−n−1∑a=0(N−a)(I+I1)RP |
(3) |
where I is the current required to drive the parasitic capacitance at a single node, N is the total number of nodes, n is the node number, and I1 is the current required to drive the load capacitance of a single node. In practical chips, in order to solve the nonlinear problem of ramp signal, the range of ramp signal is usually extended to ensure that the conversion interval of column-level ADC is within the linear interval of ramp signal.
|
I=KCP |
(4) |
|
I1=KCL |
(5) |
|
CP=WLC0 |
(6) |
|
RP=LWR0 |
(7) |
where K is the slope of the ramp signal, W is the width of the metal transmission line, C0 is the square capacitance, and R0 is the square resistance. In the CIS design process, the number of pixels, process parameters, and the slope of the ramp signal are determined at the beginning of the design. When the above parameters are determined, only the width of the metal transmission line can be designed. According to the above analysis, the width of the metal transmission line should be increased as much as possible to reduce the ramp non-uniformity error.
When the CIS is designed, all parameters related to VRAMP(n) will be determined. During the rising process of the input ramp signal, each node on the metal transmission line will generate a fixed voltage loss. Figure 3 shows the ramp signal at the each column when the slope of input ramp signal is 71.908 V/ms, the number of horizontal columns of the pixel array is 8192, the pixel size is 10 μm × 10 μm, and the width of metal transmission line is 40 μm. On the basis of the above analysis, this paper analyzes the influence mechanism of the ramp non-uniformity error on the conversion accuracy of the SS ADC. The basic working principle of the SS ADC is that the ramp signal is compared with the image signal through a comparator [26]-[29]. When the output of the comparator changes, the counter stops counting [30]-[33]. The digital output of the SS ADC is
|
DOUT=TSTART−TFLIPTCLK |
(8) |
where TSTART is the start time of counting, TFLIP is the end time of counting, and TCLK is the counting clock period.
Figure 4 shows the effect of ramp non-uniformity error on SS ADC conversion accuracy. In this operating mode, when each column-level SS ADC converts the same image signal, the ramp non-uniformity error will cause the output changes of each column-level comparator to occur at different times. This will result in different conversion results for each column-level SS ADC. Two conclusions can be drawn from the above analysis: First, in CIS, the ramp non-uniformity error is mainly manifested as a fixed voltage loss between columns, but does not affect the slope of the ramp signal. Second, in order to reduce the ramp non-uniformity error, the width of the metal transmission line should be designed to be wide enough.
In this paper, a ramp uniformity correction method is proposed based on error storage and level shifting technology. The specific circuit structure is illustrated in Figure 5, which includes four switches and two storage capacitors. The ramp uniformity correction process is divided into three stages: circuit reset, error storage and normal working. The specific operation sequence of the ramp uniformity correction method proposed in this paper is shown in Figure 6.
• Circuit reset stage. Switches S1 and S3 are turned on, and switch S2 is turned off. At this time, the voltage of the top plate and the bottom plate of the storage capacitor (CM) is VCM.
• Error storage stage. The ramp signal starts working. At time t2, the switch S3 is turned off. At this time, the voltage difference between the top and bottom plates of storage capacitors (CM) is
|
ΔV(n)=VCM−Vit2(n)=ΔV1+n−1∑a=0(N−a)(I+I1)RP |
(9) |
where Vit2 is the ramp voltage at each node of the metal transmission line at time t2, and ΔV1 is the fixed voltage offset which exceeds the ramp non-uniformity error. The determination of time t2 is related to the parasitic parameters of the metal transmission line. Reviewing the parasitic model of the metal transmission line constructed in Section III of this paper, it can be concluded that t2 is
|
t2=t1+2π(CP+CL)RPN |
(10) |
At this time, the ramp non-uniformity error of each column is stored in the storage capacitor (CM) of each column. In practice, considering the complexity of the parasitic environment, the parasitic parameters may not be accurately estimated. In this case, t2 should be chosen with a margin.
• Normal working stage. Switches S2 and S3 are turned on, and S1 is turned off. The top plate of the storage capacitor (CM) is connected to the column-level SS ADC, and the bottom plate is connected to the ramp signal. The starting voltage of ramp signal (VREF) input to the SS ADC at each column is
|
VREF(n)=VCM+ΔV(n) |
(11) |
Reviewing the conclusions drawn in Section III of this paper. The ramp non-uniformity error is mainly manifested as a fixed voltage loss between column. The error information stored on the storage capacitor (CM) can cancel the ramp non-uniformity error. At this time, the ramp signal input to each column-level SS ADC is
|
VRAMP(n)=VREF(n)+IREF×tC−n−1∑a=0(N−a)(I+I1)RP=VCM+ΔV1+IREF×tC |
(12) |
Analysis of formula (12) reveals that the ramp non-uniformity error is eliminated. It is worth stating that error storage does not need to be performed before every normal ramp cycle. In order to accurately eliminate the ramp non-uniformity error, it must be ensured that the parasitic parameters of the metal transmission line in the error storage stage are the same as those in the normal working stage. The capacitance of each column during the error storage state is
|
Ct=CM+CP+CL |
(13) |
The capacitance of each column during the normal working stage is
|
Ct=C1+CP+CL |
(14) |
To ensure that the stored ramp non-uniformity error is equal to the actual ramp non-uniformity error, C1 should be equal to CM. In order to achieve a compromise between area and performance, the storage capacitor should be selected according to the actual application requirements. In this paper, the storage capacitor CM is designed to be 1 pF, which will increase the chip area by 4mm2. For super-large array CIS, the overall chip area generally exceeds 10cm2. The ramp uniformity correction circuit proposed in this paper does not introduce static power consumption in the working phase, and only introduces dynamic power consumption when the ramp non-uniformity error is stored. According to the above analysis, the ramp uniformity correction method proposed in this paper reduces the ramp non-uniformity error without significantly increasing the chip area and introducing additional power consumption.
The ramp uniformity correction method proposed in this paper has completed the detailed circuit design and simulation verification in a 8192 (H) × 8192 (V) CMOS image sensor based on 55 nm-1P4M process. In the simulation environment built in this paper, the slope of the ramp signal is 71.908 V/ms, the pixel size is 10 μm × 10 μm, the voltage range of the ramp signal is 1.4 V, and the resolution of the ramp signal is 12-bit. Figure 7 illustrates the layout design of the column-level readout circuit. The width of the metal transmission line used to transmit the global ramp signal is designed to be 40 μm. In the layout design process, the matching between C1 and CM has been fully considered. At the same time, in order to drive large capacitive loads, the driving ability of the ramp generation circuit is enhanced. All parasitic parameters are extracted according to the actual layout.
Figure 8 shows the ramp non-uniformity error before and after correction. From the analysis of Figure 8, it can be seen that the ramp non-uniformity error is reduced from 7.89 mV to 36.8 μV in this paper. The resolution of the ramp signal designed in this paper is 12-bit, and the voltage range of the ramp signal is 1.4 V. In this case, the minimum accuracy identified by the SS ADC is 341.7 μV. In order not to degrade the SS ADC conversion accuracy, the ramp non-uniformity error cannot exceed 170.8 μV. A total of 9-runs PVT simulation is done. As shown in Figure 9, the corrected ramp non-uniformity error is always less than 170.8 μV in each case, which meets the requirements of 12-bit. A total of 200-runs Monte-Carlo simulation is done to analyze the influence of capacitance mismatch on the correction results. As shown in Figure 10, the standard deviation of the non-uniformity error is 31.763 μV, and the mean value is 34.9253 μV.
Figure 11 and Figure 12 illustrate the linearity verification results of the corrected ramp signal. At 12-bit resolution, the differential non-linearity (DNL) of the ramp signal is +0.0013/−0.004 LSB, and the integral non-linearity (INL) is +0.045/−0.021 LSB. In the application environment of super-large array CIS, with the continuous improvement of frame rate, the slope of the ramp signal will increase, which will increase the ramp non-uniformity error. In this paper, the ramp non-uniform error before and after correction is verified under different slopes. The specific simulation results are shown in Figure 13. The simulation results show that the ramp non-uniformity error increases as the slope increases, and the corrected ramp non-uniformity error is less than 170.8 μV, which meets the application requirements.
As shown in Figure 14, there is an obvious column FPN in the multi channels. Due to the ramp non-uniformity error, the gray value gradually increases from left to right, which produces stripes on the image and affects the image quality. The corrected results are also presented in Figure 14. From the simulation results, the column FPN is reduced from 1.9% to 0.01%.
Figure 15 shows the ramp non-uniformity error for multiple ramp cycles after a single error storage operation. Simulation results show that the ramp non-uniformity error is less than 1/2 LSB in 1024 ramp cycles, which meets the requirement of 12 bit application. The time consumption brought by the correction method proposed in this paper is less than 1/1000. Specifications and characteristics are summarized in Table 1.
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In this paper, a ramp uniformity correction method for super-large array CMOS image sensors is proposed, which solves the ramp non-uniformity error caused by the long metal transmission line used to transmit the global ramp signal. The detailed circuit design and comprehensive simulation verification of the proposed ramp uniformity correction method are completed based on the 55 nm-1P4M CMOS process. The voltage range of the ramp signal is 1.4 V. The slope of the ramp signal is 71.908 V/ms. The array measures 8192 (H) × 8192 (V) pixels at 10 μm pitch. The proposed correction method reduces the ramp non-uniformity error from 7.89 mV to 36 μV. The DNL and INL of the corrected ramp signal are +0.0013/−0.004 LSB and +0.045/−0.021 LSB, respectively. The ramp non-uniformity error is reduced by 99.54%. At the same time, the ramp uniformity correction method proposed in this paper ensures the high linearity of the ramp signal, does not significantly increase the chip area and introduce additional power consumption. The column FPN is reduced from 1.9% to 0.01%. It provides theoretical support for the design of super-large array CMOS image sensors.
This work was supported by the National Natural Science Foundation of China (Grant No. 62171367), the Key Research and Development Plan of Shaanxi Province (Grant No. 2021GY-060), and the Shaanxi Innovation Capability Support Project (Grant No. 2022TD-39).
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