A Design of 2-Stage Voltage Ramp-Up SRAM Physical Unclonable Function

SONG Minte; LIU Nan; ZHOU Shuaiyang; WANG Zhengguang; RU Zhanqiang; DING Peng; HUANG Wei; SONG Helun

doi:10.23919/cje.2022.00.406

Volume 33 Issue 2

Mar. 2024

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Article Navigation > Chinese Journal of Electronics > 2024 > 33(2): 371-379

Minte SONG, Nan LIU, Shuaiyang ZHOU, et al., “A Design of 2-Stage Voltage Ramp-Up SRAM Physical Unclonable Function,” Chinese Journal of Electronics, vol. 33, no. 2, pp. 371–379, 2024 doi: 10.23919/cje.2022.00.406

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Minte SONG, Nan LIU, Shuaiyang ZHOU, et al., “A Design of 2-Stage Voltage Ramp-Up SRAM Physical Unclonable Function,” Chinese Journal of Electronics, vol. 33, no. 2, pp. 371–379, 2024 doi: 10.23919/cje.2022.00.406

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A Design of 2-Stage Voltage Ramp-Up SRAM Physical Unclonable Function

doi: 10.23919/cje.2022.00.406

SONG Minte^{1, 2
,},
LIU Nan^{1, 2
,},
ZHOU Shuaiyang^{1, 2
,},
WANG Zhengguang^{1, 2
,},
RU Zhanqiang^2
,,
DING Peng^2
,,
HUANG Wei^2
,,
SONG Helun^{2
,
,}

1.
School of Nano-Tech and Nano-Bionics, University of Science and Technology of China, Hefei 230026, China
2.
Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences, Suzhou 215123, China

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Author Bio:
Minte SONG received the B.S. degree from Ocean University of China, Qingdao, China, in 2017. He is currently pursuing the Ph.D. degree in electrical engineering at University of Science and Technology of China, Hefei, China. His research interests include digital and analog integrate circuit design for physical unclonable functions (PUFs), and RISC-V ISA secure SoC design based on PUFs. (Email: mtsong2018@sinano.ac.cn)

Nan LIU received the B.S. degree in computer science and technology from Beijing Technology and Business University, Beijing, China in 2003 and the M.S. degree in precision instrument and machinery from Beihang University, Beijing China, in 2007. From 2007 to 2022, she was a Research Assistant with the Suzhou Institute of Nano-Tech and Nano-Bionics, CAS, Suzhou, China. Her research interests include the hardware design and system integration. (Email: nliu2007@sinano.ac.cn)

Shuaiyang ZHOU received the B.S. degree in microelectronics science and engineering from Soochow University, Suzhou, China, in 2021. He is currently pursuing the M.S. degree in electrical engineering at University of Science and Technology of China, Hefei, China. His research interests include analog integrated circuit design of physical unclonable functions. (Email: syzhou2022@sinano.ac.cn)

Zhengguang WANG received the B.S. degree in Communication engineering from Anhui University of Technology, Ma’anshan, China, in 2020. He is currently pursuing the M.S. degree in electrical engineering at University of Science and Technology of China, Hefei, China. His research interests include digital signal process design and FPGA implementation. (Email: zgwang2021@sinano.ac.cn)

Zhanqiang RU received the B.S. degree in physics from Qiqihar University, Qiqihar, China, in 2003 and the M.S. degrees in electronics engineering from Changchun University of Science and Technology, Changchun, China, in 2010. From 2010 to 2019, he was a Research Assistant with Suzhou Institute of Nano-Tech and Nano-Bionics (SINANO), CAS, Suzhou, China. Since 2019, he has been a Senior Engineer with the SINANO. He is the author of 8 articles, and more than 15 inventions. His research interests include non-imaging optics design and integration, frequency locking technology of diode laser. (Email: zqru2008@sinano.ac.cn)

Peng DING received the B.S. degree from Anhui University of Technology, Hefei, China, in 2017 and the M.S. degree in integrated circuit engineering from University of Science and Technology of China, Ma’anshan, China in 2020. Since 2020, he was an Assistant Engineer with the Suzhou Institute of Nano-Tech and Nano-Bionics (SINANO), CAS, Suzhou, China. His interests include the hardware design for security system and other application development and design of III-V compound semiconductor devices. (Email: pding2018@sinano.ac.cn)

Wei HUANG received the Ph.D. degree in optical engineering from Institute of Optics and Electronics, University of Science and Technology of China, Hefei, China, in 2005. He is now an Associate Researcher and M.S. supervisor of SINANO, CAS, and the Head of Laser Sensing and Imaging Laboratory. (Email: whuang2008@sinano.ac.cn)

Helun SONG received the B.S. degree in electrical engineering from the Changchun University, Changchun, China, in 2002. He received M.S. degree in optical and electrical engineering from Changchun University of Science and Technology, Changchun, China, in 2005 and the Ph.D. degree in optical engineering from Institute of Optics and Electronics, CAS, Beijing, China, in 2008. From 2008 to 2015, he was Associated Professor in Division of System Integration and IC Design, Suzhou Institute of Nano-tech and Nano-bionics (SINANO), CAS, Suzhou, China. Since 2016, he has been a Professor and Associate Administrator in Nano-Device and Materials Division, SINANO. He is the author of more than 30 articles and more than 20 inventions or utility models. His research interests include silicon based and III-V compound semiconductor device integration and application, and system of high concentration photovoltaic. (Email: hlsong2008@sinano.ac.cn)
Corresponding author: Email: hlsong2008@sinano.ac.cn
Received Date: 2022-12-01
Accepted Date: 2023-04-26

Available Online: 2023-07-15

Publish Date: 2024-03-05

Abstract

Abstract

Silicon physical unclonable function (PUF) implemented by static random access memory (SRAM) exists inherent demerit of unstable cells due to noise of environment and circuits, which significantly restricts its reproducibility. In this paper, a 16T SRAM cell with reset-delay circuit and a 2-stage voltage ramp up is fabricated and reported. Compared to conventional SRAM structure, each PUF cell adds a pair of pull-up PMOS (P-channel metal oxide semiconductor) and pull-down NMOS (N-channel metal oxide semiconductor) controlled by reset and delayed-reset signals respectively, resulting in two positive feedback stages with different amplification coefficients when the voltage is ramped up. PUF array consists of 4064 cells, 322 dummy cells and a group of 8 series-connected inverters with an area of 304 μm × 650 μm to match the digital post-processing module. PUF test chip was fabricated in HHGrace 110 nm platform with total area 1140 × 1140 μm². The average HDintra (intra-chip Hamming distance, also bit error rate, BER) and HDinter (inter-chip Hamming distance) values of the 50 PUF chips in SOP16 package measured at normal point (1.5 V/25 ℃) were 1.92% and 49.85%, respectively.
- Physical unclonable function,
- Static random access memory,
- Integrated circuits

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References(36)

References

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