A Fast Startup Crystal Oscillator with Digital SAR-AFC Based Two-Step Injection

I.   Introduction

Crystal oscillators (XOs) can convert direct current (DC) energy into alternating current (AC) one without any input signal, providing a highly accurate reference clock for other electronic systems. The excellent frequency stability of XOs stems from the high quality factor Q of the embedded quartz crystals. But high Q results in stringent energy screening and thus slow startup behavior. XOs usually take several milliseconds to turn on and settle to within 100 ppm of the final frequency, which severely increases the XO energy loss in heavily duty-cycled systems between on and off states.

To reduce the startup time, the energy injection is the most effective method. The startup time can be minimized when the injection frequency is exactly equal to the crystal resonator one. However, it is very challenging to match the injection frequency to the resonator one. The existing XOs based on single-ended or differential Pierce architecture with single or multi $g_m$ gain stage(s) apply various injection schemes [1]-[11].

The existing XO [1] uses a chirp injector (CI) and a negative resistance booster (NRB) to ensure that the injection frequency covers the resonator one via a linear frequency-modulated signal, at the cost of effective injection energy. The literature [2] based on a precisely timed energy injection (PTI) technique improves the injection frequency robustness, while degrades the design complexity and phase noise, with an amplitude regulator loop. In the XO [3], a two-step energy injection (TSI) technique based on a digital phase-locked loop (DPLL) is employed to increase the second-injection frequency accuracy, but DPLL is not easy to design, due to abundant challenging modules with a time-digital converter, a digitally controlled ring oscillator (DCO) and delay line, and a digital low-passed filter. The existing XO [4] using a dynamically-adjusted load (DAL) scheme to change the load capacitors of startup procedure is a low-cost design while the startup time is more than 200 μs. The XO [5] uses a precise dithered injection (PDI) and an active inductance (AI) for fast startup, with abundant passive resistors/capacitors and active amplifiers to degrade both power consumption and silicon area. The XO [6] employs a dithered injection (DI) to reduce the startup time, while the open-loop injection oscillator needs an external control word to ensure the injected frequency close to the resonator one. The work [7] utilizes three $g_m$ stages and a scalable self-reference chirp injection (SSCI) to speed up the startup behavior, but the startup time $\geq 400$ μs is still large.

This paper proposes a fully-digital low-cost TSI technique, by using a successive approximation register (SAR) based auto frequency control (AFC) loop, to speed up the startup behavior of XOs. The remainder of this paper is organized as follows: Section II shows the proposed XO architecture, and gives the theoretical analysis of fast startup scheme and XO parameters. In Section III, detailed design implementation is described, followed by experimental results in Section IV. Finally, conclusion is given in Section V.

II.   Proposed Architecture and Fast Startup Scheme

Figure 1 gives the proposed fast startup XO architecture using a TSI. To ensure the second-injection frequency accuracy, a fully-digital SAR-based AFC loop is used. The XO core based on a single-ended single-g_m Pierce configuration with the external 12 MHz quartz crystal (XTAL) is followed by a simplified intermediate-frequency (IF) amplifier and provides the reference clocks. The digital SAR-AFC loop generates twice energy injections for the XO core and ensures the injection frequency accuracy, and is controlled by a digital unit named time logic. Two digital tri-stage gates (TSGs) turn on/off the differential square wave injected into the crystal resonator. Multiplexer (MUX) is used to distinguish the first injection frequency (12 MHz) from the second one (192/16 = 12 MHz).

Figure  1.  Proposed fast startup XO with SAR-AFC based two-step injection.

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Figure 2 shows the time sequential waveforms generated by the time logic to conduct TSI in three domains. The counter based time logic module is activated/deactivated and outputs the enable signals for the other modules to trigger/disable the TSI, when the EN rising/falling edge arrives, respectively. For the first injection with TSGs on, the DCO in the SAR-AFC generates the coarse injection signal with the frequency around 12 MHz for the XO core, and the rest of the AFC loop are disabled. During the second domain with TSGs off, the whole AFC loop is activated and generates an accurate frequency close to 192 MHz, and the XO core without any injection signal provides 12 MHz reference clocks for the time logic and SAR-AFC loop. During the second injection with TSGs on, the DCO locks the generated 192 MHz clock, which is divided by 16 to get the 12 MHz fine injection signal into the crystal resonator, while the rest of the AFC is again disabled. After the TSI, except for the XO core and IF amplifier, all the modules are shut down and the XO quickly starts up. The first coarse injection ensures the quick reference clock generation for the SAR-AFC loop. The second fine one ensures the XO fast start up with accurate energy injection from the AFC.

Figure  2.  Time sequential waveforms for the fast startup XO.

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The XO core is designed to follow equations (1)–(3), and generates a 12 MHz reference clock. Here $L_S$ and $C_S$ are the motional inductance and capacitance of the crystal resonator, $R_S$ represents the resistive losses within the crystal, and $C_P$ is the parasitic capacitance across both terminals ($X_1$ and $X_2$) of the crystal. $p$ is the pulling factor, $R\mathrm{_{OSC}}$ is the direct DC bias resistance of $M_1$, and $f_S$ ($\omega_S$) is the crystal series resonant (angular) frequency. $V_{\mathrm{OV},M_1}$, $I_{M_1}$ and $g_m$ are the over-drive voltage, drain current and trans-conductance of $M_1$, and $f\mathrm{_{REF}}$ (i.e., the frequency of the signal $F\mathrm{_{REF}}$) is XO output frequency.

Consider the case of injecting a differential square wave with amplitude $V\mathrm{_{INJ}}$ and fundamental frequency $f\mathrm{_{inj}}$ ($\omega\mathrm{_{inj}}$) into the crystal resonator, and neglect the harmonics of the injected square wave as they are filtered by the high-$Q$ resonator. The resonator motional branch current $i_{L(t)}$ is depicted in (4)–(7). Because the quality factor $Q$ is too large relative to other values, $Q$ can be substituted into infinity to obtain (8).

With various injection frequencies, Figure 3 gives the simulated results of the resonator motional branch current, which has the frequency of $\omega_{S}$ and the sinusoidal envelope of $\mathrm{sin}[(\omega_{S}-\omega_\mathrm{inj})t/2$], with the current amplitude inversely proportional to $|\omega_{S}-\omega_\mathrm{inj}|$. When the injection time is half of the envelope period, the current amplitude reaches the maximum value. To obtain the maximum injection energy, the optimum injection time $T\mathrm{_{INJ,opt}}$ follows (9) and determines the duration ($T\mathrm{_{INJ1}}$ and $T\mathrm{_{INJ2}}$) of twice injections according to the maximum frequency error of twice injections, which is controlled by the time logic and by counting the rising edges of the reference clock $F\mathrm{_{REF}}$.

Figure  3.  Resonator motional branch currents. (a) Ideal waveform; (b) Simulated results with different injection frequencies.

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III.   Design Implementation

Figure 4 gives the proposed low-power low-cost XO core, with the conventional single-ended single-$g_m$ Pierce architecture. A constant-$g_m$ gain stage made of $M_{1\text{–}3}$, two load capacitors $C_{1\text{–}2}$ and a quartz crystal are together used to form the three-point $L_C$ resonant cavity, followed by a single-ended self-biasing band-passed IF amplifier, consisting of $C_C$, $R_C$ and $M_{1A,B}\text{–}M_{2A,B}$.

Figure  4.  Proposed XO core with the IF amplifier and XTAL model.

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A cascode current mirror is utilized to improve the frequency accuracy independent of supply voltage, and an external large resistor $R\mathrm{_{OSC}}$ ensures the DC self-biased for $g_m$ gain-stage. The 12 MHz XTAL model parameters are also shown, and the circuit design of the XO core strictly follows equations (1)–(3). The 5.6 M$\Omega$ $R\mathrm{_{OSC}}$ is depicted in (2) and off-chip to reduce hardware area. During the second domain of the XO startup procedure, where the XO core without any energy injection has a small signal amplitude at the node $X_2$, additional transistors $M_{1B}\ \mathrm{and}\; M_{2B}$ are introduced to enhance the gain of the IF amplifier to get a rail-to-rail reference clock for the activated SAR-AFC loop.

The proposed fully-digital low-complexity SAR-AFC loop is shown in Figure 5, with the timing diagram given in Figure 6, to get an accurate second-injection frequency. The 8-bit counter based frequency discriminator (FD) counts $F\mathrm{_{DCO}}$ clock rising edges during each $F\mathrm{_{FD}}$ (= 12 MHz/8) clock period and outputs the rising-edge number $Y_{7\text{–}0}$. That is, $Y_{7\text{–}0}=f\mathrm{_{DCO}}/f\mathrm{_{FD}}=8f\mathrm{_{DCO}}/ f\mathrm{_{REF}}$. When $\mathrm{EN_{SAR}}$ is high and $F\mathrm{_{SAR}}$ rising edge arrives, the 7-bit shift trigger based SAR logic compares the frequency deviation between $f\mathrm{_{DCO}}$ and $N\mathrm{_{CAL}}f\mathrm{_{FD}}$. The comparison result of $Y_{7\text{–}0}$ and $N\mathrm{_{CAL}}$ sets/clears each bit from MSB to LSB to get the desired control word $D_{6\text{–}0}$, which inversely tunes the switched-current array of DCO to offset $f\mathrm{_{DCO}}$ deviation. The FD works in odd calibration clock periods and the SAR logic works in even ones, with $90^\circ$ phase shift generated by a divider-by-8. The calibration time slot lasts about 13.25$F\mathrm{_{FD}}$ periods or 8.83 μs, that is, the SAR-AFC work time $T\mathrm{_{AFC}}$ meets (10). Once all 7 bits are generated, the FD and SAR are disabled by the time logic and the SAR output is held, until the next startup trigger arrives.

Figure  5.  Proposed fully-digital low-complexity SAR-AFC loop.

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Figure  6.  Timing diagram for the SAR-AFC loop.

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The DCO center frequency and frequency deviation conform to (11) and (12), respectively. $N\mathrm{_{CAL}}$=128 is embedded into the SAR logic and is digitally reconfigurable. In Figure 6, the original $f\mathrm{_{DCO}}$ of 249 MHz is tuned by the FD and SAR logic to the desired 192 MHz, where the frequency deviation is detected and $Y_{7\text{–}0}$ is compared to $N\mathrm{_{CAL}}$ step by step in odd periods, and the result decides each bit of $D_{6\text{–}0}$ one by one to tune $f\mathrm{_{DCO}}$ in even periods. This alternate working mode is called odd-even operation scheme and effectively improves the calibration accuracy, considering the frequency responding latency of the DCO. The proposed SAR-AFC features fully digital, low cost, high accuracy due to odd-even operation scheme, and negligible power consumption with all IF digital modules only working in a short time slot.

The proposed DCO based on a three-stage inverter-based ring configuration is shown in Figure 7, with low cost, low power consumption, wide oscillation frequency, and fair phase noise. With the fixed stage-number N and node parasitic-capacitance $C\mathrm{_{par}}$, the DCO frequency meets (13) [12] and is proportional to the charging-discharging current $I\mathrm{_{OSC}}$. The latter has two groups of currents controlled by ${\mathrm{EN}}\mathrm{_{INJ1,2}}$. The fixed one is for coarse injection frequency around 12 MHz with the worst-case deviation of 10%. And the adjustable one with the 7-bit binary switched-current array by the SAR-AFC is for fine injection frequency close to 12 MHz (=192 MHz/16) with the worst-case deviation less than 0.5%. To cover a wide frequency deviation, the DCO is designed with a tuning gain of about 1.5 MHz/LSB.

Figure  7.  Proposed low-complexity digitally controlled ring oscillator.

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IV.   Experimental Results

The proposed fast startup XO is fabricated in 65-nm CMOS, with an external 12 MHz crystal, a 5.6 M$\Omega$ resistor and two 10-pF capacitors. The chip micrograph is shown in Figure 8, with the active area of 0.02 $\mathrm{mm}^2$ and the power dissipation of 40 μW from a 1.0 V supply.

Figure  8.  Chip micrograph.

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Figure 9 gives the simulated XO transient behavior with the fast startup scheme. It is clear to claim the proposed XO conducts the TSI in three domains with different signal amplitudes (0.5/0.05/0.5/0.3 V) and oscillation frequencies (12.45/11.96/12.04/12.00 MHz), which has the similar trend as [3] and proves the presented design works well.

Figure  9.  Simulated XO transient behavior with fast startup.

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Figure 10 gives the measured XO transient behavior with the fast startup scheme. The first and second square-wave injection time are set to 0.5 and 8.4 μs, to aim at the DCO worst-case frequency deviations of 10% and 0.5%, according to (9), respectively. The SAR-AFC work time $T\mathrm{\mathrm{_{AFC}}}$ is set to 10.1 μs and meets (10). Startup time of Time Logic is 0.4 μs. That is, the total time slot of twice injections is 19.4 μs. The startup time is less than 35 μs, with the XO output frequency varying from 13.38 MHz to 12.0002 MHz step by step and settled to within 17 ppm of the final one (12 MHz). The 11.95 MHz fine injection with about 4000-ppm frequency error sets the steady-state amplitude of 0.3 V. Due to the noise from the digital SAR-AFC and the interference of the test platform, the signal amplitudes at $\mathrm{EN}$ and $X_{2}$ are distorted.

Figure  10.  Measured XO transient behavior with fast startup.

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Figure 11 shows the measured XO transient behavior without the fast startup scheme. The startup time is long and more than 2 ms. The proposed fast startup technique benefits a more than 57-fold decrease in the startup time.

Figure  11.  Measured XO transient behavior without fast startup.

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Figure 12 gives the measured XO output spectrum at the steady state, which is centered at 12 MHz and cleaned with the neglected spurs and low noise. Figure 13 illustrates the XO phase noise results at the steady state. In Figure 13, the measured and simulated phase noises of −120 dBc/Hz and −125 dBc/Hz at 1-kHz offset frequency are observed, respectively. The XO total performance is summarized and compared to the existing designs in Table 1. The simulated starting energy of the proposed scheme is 17.2 nJ within the starting time of 35 μs, including the 13.3 nJ consumption for the SAR-AFC and 3.9 nJ consumption for the XO core.

Figure  12.  Proposed fast startup XO with SAR-AFC based two-step injection.

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Figure  13.  Measured and simulated XO phase noises.

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Table  1.  XO performance summary and comparison

Parameter	This work	[1]	[2]	[3]	[4]	[5]	[6]
CMOS process (nm)	65	180	65	65	90	180	65
Supply voltage (V)	1.0	1.5	1.0	1.0	1.0	1.0	1.68
Frequency (MHz)	12	39.25	10	54	24	48	24
Startup time (μs)	35	158	10	19	$\geq$200	18	64
Startup time (cycles)	420	6201	120	1026	4800	864	1536
Startup energy (nJ)	17.2	N/A	12	34.9	36.7	114.5	N/A
Phase noise (dBc/Hz) @ 1 kHz offset	−125 to −120	−147	N/A	−139.5	N/A	−135	N/A
Load capacitor (pF)	5	>6	8	6	10	8	6
Power dissipation (μW)	40	181	45.5	198	95	180	393
Active area (mm2)	0.02	0.12	0.09	0.075	0.072	0.108	0.08
Startup technique	TSI+SAR-AFC	CI+ NRB	PTI	TSI+DPLL	DAL	PDI+AI	DI

 | Show Table

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V.   Conclusion

The proposed low-power low-cost 12-MHz XO is fabricated in 65 nm CMOS with a fully-digital fast startup scheme, using SAR-AFC based TSI technique. Measured results show the proposed design achieves 40-μW power dissipation, 0.02-mm² active area, and 35-μs startup time. The proposed fast startup scheme is a fully-digital low-cost implementation, only with the simplified FD/SAR/DCO/divider/TSG/control logic.