A High-Quality and Efficient Bus-Aware Global Router

As advanced technology nodes enter the nanometer era, the complexity of integrated circuit (IC) design is increasing, and the proportion of bus in the net is increasing. The bus routing has become a key factor affecting the performance of the chip. In addition, the existing research does not distinguish between buses and non-buses in the complete global routing process, which directly leads to the expansion of bus deviation and the degradation of chip performance. In order to solve these problems, we propose a high-quality and efficient bus-aware global router, which includes the following key strategies: 1) By introducing the routing density graph, we propose a routing model that can simultaneously consider the routability of non-buses and the deviation value of buses. 2) A dynamic routing resource adjustment algorithm is proposed to optimize the bus deviation and wirelength simultaneously, which can effectively reduce the bus deviation. 3) We propose a layer assignment algorithm consider deviation to significantly reduce the bus deviation of the 3D routing solution. 4) A DFS-based algorithm is proposed to obtain multiple routing solutions, from which the routing result with the lowest deviation is selected. Experimental results show that the proposed algorithm can effectively reduce bus deviation with the existing algorithms, so as to obtain high-quality 2D and 3D routing solutions considering bus deviation.