Volume 33 Issue 3
May  2024
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Shi CHEN, Jingyu LIU, and Li SHEN, “A Survey on Graph Neural Network Acceleration: A Hardware Perspective,” Chinese Journal of Electronics, vol. 33, no. 3, pp. 601–622, 2024 doi: 10.23919/cje.2023.00.135
Citation: Shi CHEN, Jingyu LIU, and Li SHEN, “A Survey on Graph Neural Network Acceleration: A Hardware Perspective,” Chinese Journal of Electronics, vol. 33, no. 3, pp. 601–622, 2024 doi: 10.23919/cje.2023.00.135

A Survey on Graph Neural Network Acceleration: A Hardware Perspective

doi: 10.23919/cje.2023.00.135
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  • Author Bio:

    Shi CHEN received the B.E. degree in computer science and technology from National University of Defense Technology, Changsha, China, in 2017. He is a Ph.D. candidate in the College of Computer, National University of Defense Technology, Changsha, China. His research interests include computer architecture and graph-based hardware accelerator. (Email: chenshi17@nudt.edu.cn)

    Jingyu LIU received the M.S. degree in integrated circuit engineering from National University of Defense Technology, Changsha, China, in 2021. He is a Ph.D. candidate in the College of Computer, National University of Defense Technology, Changsha, China. His research interests include computer architecture, SoC designs, and microprocessor architecture.(Email: liujingyu@nudt.edu.cn)

    Li SHEN received the B.S., M.S., and Ph.D. degrees in computer science and technology from National University of Defense Technology, Changsha, China. He is a Professor at College of Computer, National University of Defense Technology, Changsha, China. His research interests include high performance processor architecture, parallel programming, and performance optimization techniques. (Email: lishen@nudt.edu.cn)

  • Corresponding author: Email: lishen@nudt.edu.cn
  • Received Date: 2023-04-18
  • Accepted Date: 2023-08-24
  • Available Online: 2022-03-22
  • Publish Date: 2024-05-05
  • Graph neural networks (GNNs) have emerged as powerful approaches to learn knowledge about graphs and vertices. The rapid employment of GNNs poses requirements for processing efficiency. Due to incompatibility of general platforms, dedicated hardware devices and platforms are developed to efficiently accelerate training and inference of GNNs. We conduct a survey on hardware acceleration for GNNs. We first include and introduce recent advances of the domain, and then provide a methodology of categorization to classify existing works into three categories. Next, we discuss optimization techniques adopted at different levels. And finally we propose suggestions on future directions to facilitate further works.
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