An Ultra-wideband Doubler Chain with 43–65 dBc Fundamental Rejection in Ku/K/Ka Band

In this paper, a double-balanced doubler chain with >43-dBc fundamental rejection over an ultra-wide bandwidth in 0.13-μm SiGe BiCMOS technology is proposed. To achieve high fundamental rejection, high output power, and high conversion gain over an ultra-wideband, a double-balanced doubler chain with pre- and post-drivers employs a bandwidth broadening technique and a ground shielding strategy. Analysis and comparison of the single-balanced and double-balanced doublers were conducted, with a focus on their fundamental rejection and circuit imbalance. Three doublers, including a passive single-balanced doubler, an active single-balanced doubler, and a passive double-balanced doubler were designed to verify the performance and characteristics of the single- and double-balanced doublers. Measurements show that the proposed double-balanced doubler chain has approximately 15 dB better fundamental rejection, and more than twice the relative bandwidth compared to the single-balanced doubler chain fabricated with the same process. Over an 86.9% 3-dB bandwidth from 13.4 GHz to 34 GHz, the double-balanced doubler chain delivers 14.7-dBm peak output power and has >43-/33-dBc fundamental/third-harmonic rejection. To the authors’ best knowledge, the proposed double-balanced doubler chain shows the highest fundamental rejection over an ultra-wideband among silicon-based doublers at millimeter-wave frequency bands.