Comparative Analysis of Noise Margin between Pure SET-SET and Hybrid SET-PMOS Inverters

ZHANG Fan; LIU Yi; WANG Yibo; WU Minghu; HU Sheng; DONG Youli

doi:10.23919/cje.2023.00.287

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Fan ZHANG, Yi LIU, Yibo WANG, et al., “Comparative Analysis of Noise Margin between Pure SET-SET and Hybrid SET-PMOS Inverters,” Chinese Journal of Electronics, vol. 34, no. 1, pp. 1–10, 2025 doi: 10.23919/cje.2023.00.287

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Fan ZHANG, Yi LIU, Yibo WANG, et al., “Comparative Analysis of Noise Margin between Pure SET-SET and Hybrid SET-PMOS Inverters,” Chinese Journal of Electronics, vol. 34, no. 1, pp. 1–10, 2025 doi: 10.23919/cje.2023.00.287

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Comparative Analysis of Noise Margin between Pure SET-SET and Hybrid SET-PMOS Inverters

doi: 10.23919/cje.2023.00.287

ZHANG Fan^{1, 2
,},
LIU Yi^2
,,
WANG Yibo^2
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WU Minghu^{1, 2
,
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HU Sheng^2
,,
DONG Youli^2
,

1.
Hubei Key Laboratory for High-Efficiency Utilization of Solar Energy and Operation Control of Energy Storage System, Hubei University of Technology, Wuhan 430068, China
2.
School of Electrical and Electronic Engineering, Hubei University of Technology, Wuhan 430068, China

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Author Bio:
Fan ZHANG is an Associate Professor with Hubei University of Technology, Wuhan, China. Her research interests include front-end electronics, single-electron devices, and programmable devices. (Email: zhangfan@mail.hbut.edu.cn)

Yi LIU received the B.E. degree in communications from Hubei University of Technology, Wuhan, China, in 2022. She is currently pursuing the M.S. degree in new generation electronic information technology at Hubei University of Technology, Wuhan, China. Her research direction is single-electron devices and programmable devices. (Email: 3326153823@qq.com)

Yibo WANG is currently pursuing the M.S. degree in power system and automation at Hubei University of Technology, Wuhan, China, with a research focus on single event effect in semiconductor devices. (Email: m18607156232@163.com)

Minghu WU received the B.S. degree from Communication University of China, Beijing, China, and the M.S. degree from Huazhong University of Science and Technology, Wuhan, China, in 1998 and 2002, respectively. He received the Ph.D. degree from Nanjing University of Post and Telecommunications, Nanjing, China, in 2014. His major research interests include signal processing, video coding and compressive sensing. (Email: wuxx1005@163.com)

Sheng HU received the Ph.D. degree in optoelectronic information engineering from Huazhong University of Science and Technology, Wuhan, China, in 2017. Since 2018, he has been an Academic Staff Member with the School of Electrical and Electronic Engineering, Hubei University of Technology, Wuhan, China. His current research interests include design, fabrication, and characterization of optoelectronic devices and their application for optical communication and sensors. (Email: husheng@hbut.edu.cn)

Youli DONG is currently a Lecturer at Hubei University of Technology, Wuhan, China. Her research interests include hardware implementation and programmable devices. (Email: dongyouli@hbut.edu.cn)
Corresponding author: Email: wuxx1005@163.com
Received Date: 2023-08-18
Accepted Date: 2023-12-12

Available Online: 2024-02-26

Abstract

Abstract

Single-electron transistor (SET) is considered as one of the promising candidates for future electronic devices due to its advantages of low power consumption and high integration. The comparative analysis of SET-based inverters, especially the noise margin, is carried out. Pure SET-SET and hybrid SET-PMOS inverters are designed for investigation. The effects of SET supply voltage, junction resistance and junction capacitance on noise tolerance and power consumption of inverters are studied. For hybrid SET-PMOS inverters, the noise margin high (NMH) is less than 60 mV under various conditions, which may become the bottleneck of its application. For pure SET-SET inverters, both NMH and NML could reach 300 mV at a supply voltage of 0.8 V. The minimum power consumption of pure SET-SET and hybrid SET-PMOS inverters is 2.85 nW and 58 nW, respectively. The pure SET-SET inverters have greater noise tolerance and lower power consumption, which is more conducive to large-scale integration. When junction capacitance $ C_{\mathrm{J }}$ = 0.0273 aF and junction resistance $ R_{\mathrm{T}} \ge $ 1 M in SET-SET inverters at a supply voltage of 0.8 V, the NMH and NML are not significantly affected by the junction resistance and the noise margin fluctuates at 300 mV.
- Pure SET-SET,
- Hybrid SET-PMOS,
- Noise tolerance,
- Power consumption

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References(24)

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