Turn off MathJax
Article Contents
Fan ZHANG, Yi LIU, Yibo WANG, et al., “Comparative Analysis of Noise Margin between Pure SET-SET and Hybrid SET-PMOS Inverters,” Chinese Journal of Electronics, vol. x, no. x, pp. 1–10, xxxx doi: 10.23919/cje.2023.00.287
Citation: Fan ZHANG, Yi LIU, Yibo WANG, et al., “Comparative Analysis of Noise Margin between Pure SET-SET and Hybrid SET-PMOS Inverters,” Chinese Journal of Electronics, vol. x, no. x, pp. 1–10, xxxx doi: 10.23919/cje.2023.00.287

Comparative Analysis of Noise Margin between Pure SET-SET and Hybrid SET-PMOS Inverters

doi: 10.23919/cje.2023.00.287
More Information
  • Author Bio:

    Fan ZHANG is an Associate Professor with Hubei University of Technology, Wuhan, China. Her research interests include Front-end electronics, Single-electron devices, and Programmable devices. (Email: zhangfan@mail.hbut.edu.cn)

    Yi LIU received the B.E. degree in Communications from Hubei University of Technology in 2022 and is a postgraduate student at Hubei University of Technology majoring in New Generation Electronic Information Technology. Her research direction is Single-electron devices and Programmable devices. (Email: 3326153823@qq.com)

    Yibo WANG is currently an M.S. candidate at Hubei University of Technology, majoring in Power System and Automation, with a research focus on Single Event Effect in semiconductor devices. (Email: m18607156232@163.com)

    Minghu WU received the B.S. degree from Communication University of China and the M.S. degree from Huazhong University of Science and Technology in 1998 and 2002, respectively. He received Ph.D. degree from Nanjing University of Post and Telecommunications in 2014. His major research interests include signal processing, video coding and compressive sensing. (Email: wuxx1005@163.com)

    Sheng HU received his Ph.D. in Optoelectronic Information Engineering from Huazhong University of Science and Technology, in 2017. Since 2018, he has been an academic staff member with the School of Electrical and Electronic Engineering, Hubei University of Technology. His current research interests include design, fabrication, and characterization of optoelectronic devices and their application for optical communication and sensors. (Email: husheng@hbut.edu.cn)

    Youli DONG is currently a Lecturer at Hubei University of Technology, Wuhan,China. Her research interests include hardware implementation and Programmable devices. (Email: dongyouli@hbut.edu.cn)

  • Corresponding author: Email: wuxx1005@163.com
  • Received Date: 2023-08-18
  • Accepted Date: 2023-12-12
  • Available Online: 2024-02-26
  • Single-electron transistor (SET) is considered as one of the promising candidates for future electronic devices due to its advantages of low power consumption and high integration. The comparative analysis of SET-based inverters, especially the noise margin, is carried out. Pure SET-SET and hybrid SET-PMOS inverters are designed for investigation. The effects of SET supply voltage, junction resistance and junction capacitance on noise tolerance and power consumption of inverters are studied. For hybrid SET-PMOS inverters, the noise margin high (NMH) is less than 60 mV under various conditions, which may become the bottleneck of its application. For pure SET-SET inverters, both NMH and NML could reach 300 mV at a supply voltage of 0.8 V. The minimum power consumption of pure SET-SET and hybrid SET-PMOS inverters is 2.85 nW and 58 nW, respectively. The pure SET-SET inverters have greater noise tolerance and lower power consumption, which is more conducive to large-scale integration. When junction capacitance $ C_J $ = 0.0273aF and junction resistance $ R_T \ge $ 1M in SET-SET inverters at a supply voltage of 0.8 V, the NMH and NML are not significantly affected by the junction resistance and the noise margin fluctuates at 300 mV.
  • loading
  • [1]
    H. Iwai, “Future of nano CMOS technology,” in Proceedings of 2014 IEEE International Conference on Electron Devices and Solid-State Circuits, Chengdu, China, pp. 1–3, 2014.
    [2]
    A. P. Jacob, R. L. Xie, M. G. Sung, et al., “Scaling challenges for advanced CMOS devices,” International Journal of High Speed Electronics and Systems, vol. 26, no. 01n02, 2017. doi: 10.1142/S0129156417400018
    [3]
    K. Kuhn, C. Kenyon, A. Kornfeld, et al., “Managing process variation in Intel’s 45 nm CMOS technology,” Intel Technology Journal, vol. 12, no. 2, pp. 93–109, 2008.
    [4]
    W. H. Krautschneider, A. Kohlhase, and H. Terletzki, “Scaling down and reliability problems of gigabit CMOS circuits,” Microelectronics Reliability, vol. 37, no. 1, pp. 19–37, 1997. doi: 10.1016/0026-2714(96)00236-3
    [5]
    D. Goldhaber-Gordon, J. Göes, H. Shtrikman, et al., “The Kondo effect in a single-electron transistor,” in Kondo Effect and Dephasing in Low-Dimensional Metallic Systems, V. Chandrasekhar, C. Haesendonck, A. Zawadowski, Eds. Springer, Dordrecht, Netherlands, pp. 163–170, 2001.
    [6]
    S. Mahapatra, V. Vaish, C. Wasshuber, et al., “Analytical modeling of single electron transistor for hybrid CMOS-SET analog IC design,” IEEE Transactions on Electron Devices, vol. 51, no. 11, pp. 1772–1782, 2004. doi: 10.1109/TED.2004.837369
    [7]
    K. U. K. Uchida, K. M. K. Matsuzawa, J. K. J. Koga, et al, “Analytical single-electron transistor (SET) model for design and analysis of realistic SET circuits,” Japanese Journal of Applied Physics, vol. 39, no. 4S, article no. 2321, 2000. doi: 10.1143/JJAP.39.2321
    [8]
    G. Lientschnig, I. Weymann, and P. Hadley, “Simulating hybrid circuits of single-electron transistors and field-effect transistors,” Japanese Journal of Applied Physics, vol. 42, no. 10R, pp. 6467–6472, 2003. doi: 10.1143/JJAP.42.6467
    [9]
    T. Gyakushi, I. Amano, A. Tsurumaki-Fukuchi, et al., “Double-gate operation of metal nanodot-array-based single-electron device,” 2022.
    [10]
    J. Y. Fang, X. X. Li, W. K. Xie, et al., “A novel fabrication of single electron transistor from patterned gold nanoparticle array template-prepared by polystyrene nanospheres,” Nanomaterials, vol. 12, no. 18, article no. 3102, 2022. doi: 10.3390/nano12183102
    [11]
    H. Ali, J. Tang, K. Peng, et al., “Single-electron pumping in a ZnO single-nanobelt quantum dot transistor,” Science China Physics, Mechanics & Astronomy, vol. 63, no. 6, article no. 267811, 2020. doi: 10.1007/s11433-019-1494-4
    [12]
    A. Samanta, M. Muruganathan, M. Hori, et al., “Single-electron quantization at room temperature in a-few-donor quantum dot in silicon nano-transistors,” Applied Physics Letters, vol. 110, no. 9, article no. 093107, 2017. doi: 10.1063/1.4977836
    [13]
    R. Shah and R. Dhavse, “Novel hybrid silicon SETMOS design for power efficient room temperature operation,” Silicon, vol. 13, no. 2, pp. 587–597, 2021. doi: 10.1007/s12633-020-00461-x
    [14]
    S. Banik, R. Trivedi, A. Kalavadiya, et al., “A single electron transistor-based floating point multiplier realization at room temperature operation,” in Select Proceedings of the Fourth International Conference on Emerging Technology Trends in Electronics, Communication and Networking, pp. 39–48, 2023.
    [15]
    B. Mishra, V. Singh Kushwah, and R. Sharma, “Power consumption analysis of MOSFET and single electron transistor for inverter circuit,” Materials Today:Proceedings, vol. 47 pp. 6600–6604, 2021. doi: 10.1016/j.matpr.2021.05.094
    [16]
    T. Tanamoto and K. Ono, “Simulations of hybrid charge-sensing single-electron-transistors and CMOS circuits,” Applied Physics Letters, vol. 119, no. 17, article no. 174002, 2021. doi: 10.1063/5.006855
    [17]
    J. G. Guimarães and B. de Oliveira Câmara, “Digital circuits and systems based on single-electron tunneling technology,” Journal of Integrated Circuits and Systems, vol. 16, no. 1, pp. 1–9, 2021. doi: 10.29292/jics.v16i1.475
    [18]
    D. Griveau, S. Ecoffey, R. M. Parekh, et al., “Single electron CMOS-like one bit full adder,” in Proceedings of the 13th International Conference on Ultimate Integration on Silicon (ULIS), Grenoble, France, pp. 77–80, 2012.
    [19]
    J. E. Brewer, “Computational single electronics [book review],” IEEE Circuits and Devices Magazine, vol. 20, no. 1, article no. 5, 2004. doi: 10.1109/MCD.2004.1263400
    [20]
    U. Hashim, A. Rasmi, and S. Sakrani, https://api.semanticscholar.org/, 2007.
    [21]
    I. O. Kulik and R. I. Shekhter, “Kinetic phenomena and charge discreteness effects in granulated media,” Journal of Experimental and Theoretical Physics, vol. 41, no. 2, pp. 308–316, 1975.
    [22]
    A. Sarmiento-Reyes, F. J. Castro González, and L. Hernández-Martínez, “A methodology for simulation of hybrid single-electron/mos transistor circuits,” Superficies y Vacío, vol. 26, no. 2, pp. 42–49, 2013.
    [23]
    G. W. Hanson, https://api.semanticscholar.org/, 2008.
    [24]
    S. M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design. The McGraw-Hill Companies, New York, NY, USA, 1996.
  • 加载中

Catalog

    通讯作者: 陈斌, bchen63@163.com
    • 1. 

      沈阳化工大学材料科学与工程学院 沈阳 110142

    1. 本站搜索
    2. 百度学术搜索
    3. 万方数据库搜索
    4. CNKI搜索

    Figures(10)  / Tables(7)

    Article Metrics

    Article views (55) PDF downloads(3) Cited by()
    Proportional views
    Related

    /

    DownLoad:  Full-Size Img  PowerPoint
    Return
    Return