14-bit SAR ADC with On-Chip Digital Bubble Sorting Calibration Technology

FAN Hua; CHEN Zhuorui; XU Tongrui; Maloberti Franco; WEI Qi; FENG Quanyuan

doi:10.23919/cje.2023.00.307

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Article Navigation > Chinese Journal of Electronics > 2024 > Accepted Manuscript

Hua FAN, Zhuorui CHEN, Tongrui XU, et al., “14-bit SAR ADC with On-Chip Digital Bubble Sorting Calibration Technology,” Chinese Journal of Electronics, vol. x, no. x, pp. 1–12, xxxx doi: 10.23919/cje.2023.00.307

Citation:

Hua FAN, Zhuorui CHEN, Tongrui XU, et al., “14-bit SAR ADC with On-Chip Digital Bubble Sorting Calibration Technology,” Chinese Journal of Electronics, vol. x, no. x, pp. 1–12, xxxx doi: 10.23919/cje.2023.00.307

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14-bit SAR ADC with On-Chip Digital Bubble Sorting Calibration Technology

doi: 10.23919/cje.2023.00.307

FAN Hua^{1, 2, 3
,
,},
CHEN Zhuorui^1
,,
XU Tongrui^1
,,
Maloberti Franco^4
,,
WEI Qi^5
,,
FENG Quanyuan^6
,

1.
University of Electronic Science and Technology of China (UESTC), Chengdu 610054, China
2.
Institute of Electronic and Information Engineering of UESTC in Guangdong, UESTC, Dongguan 523808, China
3.
Chongqing Institute of Microelectronics Industry Technology, UESTC, Chongqing 401331, China
4.
Department of Electrical, Computer, and Biomedical Engineering, University of Pavia, Pavia 27100, Italy
5.
Department of Precision Instrument, Tsinghua University, Beijing 100084, China
6.
School of Information Science and Technology, Southwest Jiaotong University, Chengdu 610031, China

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Author Bio:
Hua FAN (M16) was born in Ziyang, Sichuan, China. She received the B.S. degree in communications engineering and the M.S. degree in computer science and technology from Southwest Jiaotong University, Chengdu, China, in 2003 and 2006, respectively, and the Ph.D. degree from Tsinghua University, Beijing, China, in July 2013. From September 2013 to June 2016, she was an Assistant Professor with the University of Electronic Science and Technology of China, Chengdu, and an Associate Professor from July 2016 to July 2021, where she has been a Full Professor since July 2021. She has authored over 100 articles in peer reviewed journals (e.g. IEEE Trans. Circuits and Systems I, IEEE Trans. Circuits and Systems II, and IEEE Sensors Journal, etc) and in international conferences. (Email: fanhua7531@163.com)

Zhuorui CHEN was born in Shenzhen, Guangdong, China, in 2001. He received the B.S. degree in electrical engineering from the University of Electronic Science and Technology of China (UESTC), Chengdu, China, in 2023, where he is currently pursuing the M.S. degree in Integrated Circuit Engineering. His research interests include analog circuit design,and mixed-signal integrated circuits design, with a special focus on high-precision successive-approximation-register (SAR) analog-to-digital converters (ADCs). (Email: 1791014526@qq.com)

Tongrui XU was born in Luoyang, Henan, China, in 1999. She received a B.S. degree from the University of Electronic Science and Technology of China (UESTC), Chengdu, China, in 2021. She is currently a postgraduate in, Chengdu, China. From 2021 to the present, she was an undergraduate research assistant under the supervision of Mrs. Hua Fan, UESTC, Chengdu, China. Her research interest is in analog circuit design,and mixed-signal integrated circuits design, with a special focus on high-precision successive-approximation-register (SAR) analog-to-digital converters (ADCs). (Email: 1104022033@qq.com)

Franco Maloberti (M'84–SM'87–F'96–LF'16) received the Laurea Degree in Physics (Summa cum Laude) from the University of Parma, Italy, and the Dr. Honoris Causa degree in Electronics from the Inaoe, Puebla, Mexico. He is IEEE Life Fellow and was a Visiting Professor at ETH-PEL, Zurich and at EPFL-LEG, Lausanne. He was the TI/J. Kilby Analog Engineering Chair Professor at the Texas AM University and Chair Professor at the University of Texas at Dallas. He is an Emeritus Professor at the University of Pavia, Italy. He is an Honorary Professor, University of Macau, China. His professional expertise is in the design, analysis and characterization of integrated circuits and analog-digital applications, mainly in the areas of switched capacitor circuits, data converters, interfaces for telecommunication and sensor systems, and CAD for analog and mixed A-D design. He has written more than 600 published papers, seven books and holds 36 patents. He is the Chairman of The Academic Committee of the AMSV Key Lab, Macau, and Honorary Professor at the University of Macau, China. (Email: franco.maloberti@unipv.it)

Qi WEI was born in Ningxia province, in 1983. He received the B.S. degree in electrical engineering, from Northwestern Polytechnical University, XiAn, in 2005. He received the Ph.D. degree from Tsinghua University, Beijing, in 2010. He is currently an associate professor of Department of Precision Instrument of Tsinghua University. His research interests focus on analog IC design and high-performance data converter, including Pipeline ADC, SAR ADC, and current steer DAC. (Email: weiqi@tsinghua.edu.cn)

Quanyuan FENG received the M.S. degree in microelectronics and solid electronics from the University of Electronic Science and Technology of China, Chengdu, China, in 1991, and the Ph.D. degree in electromagnetic field and microwave technology from Southwest Jiaotong University, Chengdu, in 2000. He is currently the Head of the Institute of Microelectronics, Southwest Jiaotong University. His current research interests include integrated circuits design, RFID technology, embedded system, wireless communications, antennas and propagation, microwave and millimeter-wave technology, smart information processing, electromagnetic compatibility, and RF/microwave devices and materials. (Email: fengquanyuan@163.com)
Corresponding author: Email: fanhua7531@163.com
Available Online: 2024-03-07

Abstract

Abstract

This article designs a 14-bit successive approximation register analog-to-digital converter (SAR ADC). A novel digital bubble sorting calibration method is proposed and applied to eliminate the effect of capacitor mismatch on the linearity of the SAR ADC. To reduce the number of capacitors, a hybrid architecture of a high 8-bit binary-weighted capacitor array and a low 6-bit resistor array is adopted by the DAC. The $ \rm V_{CM} $-based switching scheme is chosen to reduce the switching energy and area of the DAC. The time-domain comparator is employed to obtain lower power consumption. Sampling is performed through a gate voltage bootstrapped switch to reduce the nonlinear errors introduced when sampling the input signal. Moreover, the SAR logic and the whole calibration is totally implemented on-chip through digital IC tools such as Design Compiler (DC), IC compiler (ICC), etc. Finally, a prototype is designed and implemented using 0.18 μm BCD 1.8 V Complementary Metal Oxide Semiconductor (CMOS) technology. The measurement results show that the SAR ADC with on-chip bubble sorting calibration method achieves the signal-to-noise-and-distortion ratio (SNDR) of 69.75 dB and the spurious-free dynamic range (SFDR) of 83.77 dB.
- Analog-to-digital converter (ADC),
- Successive approximation register (SAR),
- Digital calibration,
- Bubble sorting

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References(29)

References

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