14-bit SAR ADC with On-Chip Digital Bubble Sorting Calibration Technology

This article designs a 14-bit successive approximation register analog-to-digital converter (SAR ADC). A novel digital bubble sorting calibration method is proposed and applied to eliminate the effect of capacitor mismatch on the linearity of the SAR ADC. To reduce the number of capacitors, a hybrid architecture of a high 8-bit binary-weighted capacitor array and a low 6-bit resistor array is adopted by the digital-to-analog (DAC). The common-mode voltage V_CM-based switching scheme is chosen to reduce the switching energy and area of the DAC. The time-domain comparator is employed to obtain lower power consumption. Sampling is performed through a gate voltage bootstrapped switch to reduce the nonlinear errors introduced when sampling the input signal. Moreover, the SAR logic and the whole calibration is totally implemented on-chip through digital integrated circuit (IC) tools such as Design Compiler, IC compiler, etc. Finally, a prototype is designed and implemented using 0.18 μm Bipolar-complementary metal oxide semiconductor (CMOS)-double-diffused MOS 1.8 V CMOS technology. The measurement results show that the SAR ADC with on-chip bubble sorting calibration method achieves the signal-to-noise-and-distortion ratio of 69.75 dB and the spurious-free dynamic range of 83.77 dB.