A Novel SEC-DED-DAEC Algorithm with Zero Error Rate

In harsh environments like space, Multiple Cell Upsets (MCUs) severely threaten the reliability of on-chip memories. While Single Error Correction-Double Error Detection-Double Adjacent Error Correction (SEC-DED-DAEC) codes are effective against adjacent double-bit errors, a critical challenge remains: many existing implementations are prone to miscorrecting certain non-adjacent double-bit errors, creating a reliability vulnerability. Furthermore, current solutions often suffer from poor scalability or significant hardware overhead. This paper addresses these challenges by proposing a novel SEC-DED-DAEC algorithm that guarantees a zero error rate for all double-bit errors. The proposed algorithm is highly scalable, capable of generating optimized check matrices for data widths ranging from 8 to 512 bits. Through a systematic construction and optimization process, our approach not only eliminates miscorrection but also reduces redundancy. Compared to state-of-the-art zero-error-rate SEC-DED-DAEC schemes, our method requires fewer check bits, demonstrates superior scalability, and, as verified by hardware synthesis, results in lower area, latency, and power consumption in its encoder and decoder circuits.