Co-optimization of Dynamic/Static Test Power inScan Test

Low-power design has become a challengeof test. We propose an effective low-power scan architecture named PowerSluice to minimize power consumptionduring scan test, which is based on scan chain modifications. On one hand, a kind of blocking logic is insertedinto the scan chain to reduce the dynamic power and twokinds of controlling units are also inserted to decrease theleakage power during the shift cycle. On the other hand,using genetic algorithm, the exact values of control signalsare found out to control the process. Experiments resultsindicate that this architecture can effectually reduce powerduring scan test with probably minimum area cost.