HiSCA: Overcoming the Limitation of Clustered Unicore Processors Through Hardware/Software Codesign

The partitioning of resources such as pipelines and register files among clusters has been proven to be an effective way to improve performance and scalability. However, improvements are limited by traditional binary instruction encoding schemes and centralized instruction execution control mechanism. Meanwhile, clustered processors may come at the cost of performance degradation due to limited data locality resulted from a lack of available registers and functional units. This paper introduces a Highly scalable clustered architecture (HiSCA) to improve the scalability and performance of clustered processors. The hardware/software instruction encoding scheme of HiSCA splits the instruction stream into chains of instructions (packs) and encodes common information within the same packs in dedicated instruction words, thus reducing the amount of information encoded in instruction words. The pipeline of HiSCA, which features in-order issuing, out-of-order execution and parallel but in-order commitment, release instruction issuing from the heavy burden of dynamic scheduling, and allows functional units to fetch data and manage their own execution. HiSCA scales efficiently to 32 clusters with 1024 general purpose registers. Experimental results also show that, for a 4- cluster/8-issue configuration, HiSCA can achieve an average of 13.3% performance speedup and a 4.6% improvement in frequency with minimal hardware overhead, as compared to a traditional clustered processor with nearly the same hardware complexity.