The novel technique for effcient implementation of Field programmable gate array (FPGA)based wave-pipelined Coordinate rotation digital computer(CORDIC) algorithm is presented in this paper. A newclock adjustment scheme which permits finer tuning ofthe skew between on-chip clocks is developed. All datain FPGA-based Wave pipelined CORDIC circuit (WPCC)pass through the same number of logic gates, and all pathsare routed using identical routing resources for achievingbest path balancing. Experimental results show that a 256LUT logic depth WPCC mapped on XC2V6000-4 runs ashigh as 256 MHz, which is a little slower than the speedof 262 MHz based on the 16-stage Conventional pipelinedCORDIC circuit (CPCC) in the same chip. But the latency of the WPCC is 39.1 ns, which is 36% shorter thanthe latency of 16 clock cycles (i.e. 61.1 ns in this example)of 16-stage CPCC.