Statistical Analysis of Full-Chip Leakage Powerfor 65nm CMOS Node and Beyond

In this paper we address the growing issue of statistical full-chip leakage power analysis for 65nmCMOS node and beyond at the circuit level. Specifically, we first develop a fast approach to analyze the statedependent total leakage power of a large circuit block,considering junction tunneling leakage (I_junc), subthresholdleakage (I_sub), and gate oxide leakage (I_gate). We then propose our algorithm to estimate the full-chip leakage powerwith consideration of both Gaussian and non-Gaussian parameter distributions, capturing spatial correlations using a grid-based model. The proposed approach is implemented and compared with Monte Carlo simulationson ISCAS85 benchmark circuits and shows high accuracy.Comparison with measurement results of SRAMs is alsolisted to demonstrate the significance of our method. Fora circuit with G gates, the complexity of our approach isO(G).