NBTI-aware Dual V_th Assignment for Leakage Reduction and Lifetime Assurance

Negative bias temperature instability(NBTI), which causes temporal performance degradationin digital circuits by affecting PMOS threshold voltage,has become the dominant circuit lifetime reliability factor.Design for lifetime reliability, especially for NBTI-inducedcircuit performance degradation, is emerging as one of themajor design concerns. In this paper, an NBTI-aware dualV_th assignment is for the first time proposed to simultaneously reduce the circuit leakage current and ensure thecircuit lifetime requirement. Our experimental results onISCAS85 benchmark show that the NBTI-aware dual V_thassignment not only assigns more high V_th gates in the ISCAD85 circuits and leads to up to 14.88% (average 3.46%)further leakage saving under 5% circuit performance relaxation, but also brings different optimal high V_th (on average11mV higher) without performance relaxation.