WANG Yu, LUO Hong, HE Ku, et al., “NBTI-aware Dual Vth Assignment for Leakage Reduction and Lifetime Assurance,” Chinese Journal of Electronics, vol. 18, no. 2, pp. 225-230, 2009,
Citation:
WANG Yu, LUO Hong, HE Ku, et al., “NBTI-aware Dual Vth Assignment for Leakage Reduction and Lifetime Assurance,” Chinese Journal of Electronics, vol. 18, no. 2, pp. 225-230, 2009,
WANG Yu, LUO Hong, HE Ku, et al., “NBTI-aware Dual Vth Assignment for Leakage Reduction and Lifetime Assurance,” Chinese Journal of Electronics, vol. 18, no. 2, pp. 225-230, 2009,
Citation:
WANG Yu, LUO Hong, HE Ku, et al., “NBTI-aware Dual Vth Assignment for Leakage Reduction and Lifetime Assurance,” Chinese Journal of Electronics, vol. 18, no. 2, pp. 225-230, 2009,
Negative bias temperature instability(NBTI), which causes temporal performance degradationin digital circuits by affecting PMOS threshold voltage,has become the dominant circuit lifetime reliability factor.Design for lifetime reliability, especially for NBTI-inducedcircuit performance degradation, is emerging as one of themajor design concerns. In this paper, an NBTI-aware dualVth assignment is for the first time proposed to simultaneously reduce the circuit leakage current and ensure thecircuit lifetime requirement. Our experimental results onISCAS85 benchmark show that the NBTI-aware dual Vthassignment not only assigns more high Vth gates in the ISCAD85 circuits and leads to up to 14.88% (average 3.46%)further leakage saving under 5% circuit performance relaxation, but also brings different optimal high Vth (on average11mV higher) without performance relaxation.