An innovative design is presented whichimplements an area and power efficient near-lossless image compressorin an ASIC for power-constrained image sensor nodes in medical fieldsuch as the wireless endoscope capsule. The compressor is composed of aJPEG-LS encoder with a novel hardware-oriented image filter whichimproves the average compression by 17.3%. Architecture designtechniques such as parallel pipelines and in-stage resource sharing areextremely employed to save the die area. Low power design techniquessuch as hierarchy memory access, clock gating and voltage scaling areused to reduce power consumption. The compressor occupies a die area of0.85mm2 in 0.18m 1P6M CMOS technology. The implementedJPEG-LS encoder costs the lowest gate counts and memory requirement inthe reported literature. For VGA images at 15 frames per second, thereal-time compression can be achieved at 20MHz clock frequency withpower dissipation of 800uW at 1.1V supply voltage.