TransARM: An Efficient Instruction Set Architecture Emulator

Instruction set architecture (ISA) emulation is the key to implement a virtual machine across different ISAs. This paper presents the design and implementation of TransARM, an efficient ISA emulator supporting IA-32 applications on ARM-based systems. TransARM adopts interpretation and binary translation as its basis. Interpretation is performed at the initial stage of emulation. Translation is performed only on the hot spots. Lazy flag updating and Pcache-based hybrid threaded interpretation is used to improve the interpretation performance while superblock chaining is used to accelerate binary translation. Several implementation issues which are crucial in the design of an ISA emulator are discussed, such as the executable and linking format resolution, architecture mapping and system call emulation. Benchmarks selected from MiBench are emulated by TransARM on two real ARM-based systems. Experimental results demonstrate the correctness of TransARM in terms of ISA emulation and indicate that TransARM is competitive to other ISA emulators.