Efficient Scheme for Path Recognition fromIntegrated Circuit Layout

YUAN Zhaohui; SUN Shilei; WANG Gaofeng

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Article Navigation > Chinese Journal of Electronics > 2010 > 19(4): 627-630

YUAN Zhaohui, SUN Shilei, WANG Gaofeng, “Efficient Scheme for Path Recognition fromIntegrated Circuit Layout,” Chinese Journal of Electronics, vol. 19, no. 4, pp. 627-630, 2010,

Citation:

YUAN Zhaohui, SUN Shilei, WANG Gaofeng, “Efficient Scheme for Path Recognition fromIntegrated Circuit Layout,” Chinese Journal of Electronics, vol. 19, no. 4, pp. 627-630, 2010,

YUAN Zhaohui, SUN Shilei, WANG Gaofeng, “Efficient Scheme for Path Recognition fromIntegrated Circuit Layout,” Chinese Journal of Electronics, vol. 19, no. 4, pp. 627-630, 2010,

Citation:

YUAN Zhaohui, SUN Shilei, WANG Gaofeng, “Efficient Scheme for Path Recognition fromIntegrated Circuit Layout,” Chinese Journal of Electronics, vol. 19, no. 4, pp. 627-630, 2010,

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Efficient Scheme for Path Recognition fromIntegrated Circuit Layout

Received Date: 2009-08-01
Rev Recd Date: 2010-03-01
Publish Date: 2010-11-25

Abstract

Abstract

An efficient scheme for the centerline-basedpath recognition from an IC mask layout is presented. Unlikethe division-based methods, a tree-traverse-based approachis proposed. This new scheme can be realized as areverse procedure of the layout generation from wire routingtrees. Moreover, this scheme can handle complex allanglewires. Experimental results show that this schemehas nearly linear computational complexity yet generatesprecise results.
- VLSI,
- Mask layout,
- Path recognition,
- Interconnect extraction