The Energy Optimization for Architectures withLimited Addressing Modes Using Scratch-PadMemory

Low power design plays a very importantrole in the modern embedded system. Compared withtraditional cache, many researchers focus on the substitute:Scratch-pad memory, which can reduce energy consumptionand guarantee the overall performance. However,few of these optimization schemes took architectureswith limited addressing modes into consideration, whichmeans ignoring the long-branch overheads existing in almostall of Reduced instruction set computer (RISC) architectures.This paper implements two matrices to illustratethose overheads quantitatively, and eventually figuresout, in virtue of our improved knapsack algorithm and itscorresponding dynamic programming, the most optimizedimage layout for energy considerations. Compared withgeneral SPM optimization method, experiments achieve upto 58.6% and average 19.5% decrease in energy consumptionwithout any performance degradation when SPM sizeis only 8kbytes.