Slice Analysis Based Bayesian Power Model forSequential Circuits
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Graphical Abstract
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Abstract
Bayesian modeling method and slice anal-
ysis techniques show good e®ect in cycle-accurate power
analysis of combinational circuit. In this paper, we use vir-
tual signal logical depth assignment to resolve the problem
that signal loop can not be sliced in sequential circuits.
With this method, we build cycle-accurate power model
based on Bayesian inference and slice analysis techniques.
The experiments on ISCAS89 benchmark show that the
power-per-cycle estimation error is 6.7%. By analyzing the
relation between error trend under di®erent slices and cir-
cuit's size, we also build a thumb rule about how to choose
best slice number: when the accumulative gate number
is about 73% of total gate number, the model error with
slice-based parameters usually arrives minimum value.
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