As transistors get smaller and approach technological limits, they suffer from increased susceptibility to failures due to wearout. Future multi-core processors will have many cores, but with decreased service life due to manufacturing variability and high operating temperatures from high power densities. This poses a problem as complex systems with many less reliable cores operate at high temperatures over time, and a small failure can yield unpredictable results in software. However, for network processing applications, processor wearout failure can be mitigated in a gracefully degradable way by taking advantage of the predictable and fault tolerant nature of packet processing. A fault-tolerant asymmetric core arrangement is proposed to improve overall system dependability, useful life and performance, and a SPN model used to predict performability. System throughput and availability is predicted under various loads, as well as long term packet processing behavior.