Peter D. Ungsunan, LIN Chuang, KONG Xiangzhen. Wearout Tolerant Network Processing on Asymmetric Multi-core Processor[J]. Chinese Journal of Electronics, 2011, 20(1): 35-38.
Citation: Peter D. Ungsunan, LIN Chuang, KONG Xiangzhen. Wearout Tolerant Network Processing on Asymmetric Multi-core Processor[J]. Chinese Journal of Electronics, 2011, 20(1): 35-38.

Wearout Tolerant Network Processing on Asymmetric Multi-core Processor

  • Received Date: 2010-02-01
  • Rev Recd Date: 2010-05-01
  • Publish Date: 2011-01-05
  • As transistors get smaller and approach technological limits, they suffer from increased susceptibility to failures due to wearout. Future multi-core processors will have many cores, but with decreased service life due to manufacturing variability and high operating temperatures from high power densities. This poses a problem as complex systems with many less reliable cores operate at high temperatures over time, and a small failure can yield unpredictable results in software. However, for network processing applications, processor wearout failure can be mitigated in a gracefully degradable way by taking advantage of the predictable and fault tolerant nature of packet processing. A fault-tolerant asymmetric core arrangement is proposed to improve overall system dependability, useful life and performance, and a SPN model used to predict performability. System throughput and availability is predicted under various loads, as well as long term packet processing behavior.
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      沈阳化工大学材料科学与工程学院 沈阳 110142

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