VLSI Design of FC-1 and FC-2 in Fiber Channel
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Graphical Abstract
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Abstract
Fiber channel (FC) has become a major
technology in Storage area network (SAN), especially in
enterprise datacenters. In this paper, we propose a con¯g-
urable and all-around architecture to implement the FC-1
and FC-2 layers in VLSI. The speed negotiation algorithm
is also implemented in hardware to automatically switch
speed among 4 di®erent speeds. In order to achieve the
on-the-°y processing speed, we utilize the hardware to ac-
celerate the processing of FC-1 and part of FC-2. The
prototype chip is fabricated in a 0.18um CMOS technol-
ogy and the core occupies an area of 7:1£8mm2. The chip
has been validated to be fully functional and can achieve
173MBps processing performance.
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