A Robust High Density 7T SRAM Bitcell for Subthreshold Applications

In this paper, a robust high density 7T subthreshold SRAM bitcell is proposed for ultra low voltage (200 mV) applications. Dual-ended write and single-ended read operation ensures high read static noise margin of SRAM bitcell without the expense of writability. Combined with partial dynamic threshold MOSFET technique, 7T SRAM exhibits both robust and density efficiency, making the design less vulnerable to process variation with less area penalty. Compared to the referenced 6T and 8T SRAM bitcell, the proposed bitcell has four aspects of improvement: (1) 5.13% and 7.27% larger hold margin, (2) 80.60% and 51.92% of hold margin standard deviation, (3) 28.58% and 46.28% reduction of bitcell area, and (4) 16X and 8X number of bitcells per bitline (at 200 mV).