This paper presents a nonlinear dynamic bandwidth control algorithmfor Digitally controlled phaselocked loop (DCPLL). Because of nonlinear relationship between sensed phase error and feedback clock frequency, there are many erroneous bandwidth adjustment in the PLL with traditional dynamic bandwidth control algorithm. The proposed algorithm adjusts the DCPLL bandwidth when small phase error has been sensed several times by the phase detector, thus it avoids unnecessary bandwidth adjustment. To verify the feasibility of the proposed algorithm, we develop a behavioral model in Matlab. Simulation results show that the DCPLL locking time using the proposed algorithm is reduced to 28.6% to 85.7% compared with the DCPLL employing the traditional algorithm. Finally, a DCPLL is implemented by CSM 0.18μm 1P6M CMOS. The measured results show that the DCPLL without the proposed algorithm will spend extra 2.5μs when locking to 550MHz.