CUI Wei, WU Siliang. Digital Random Sequence Generation Algorithmand VLSI Implementation[J]. Chinese Journal of Electronics, 2010, 19(2): 351-355.
Citation: CUI Wei, WU Siliang. Digital Random Sequence Generation Algorithmand VLSI Implementation[J]. Chinese Journal of Electronics, 2010, 19(2): 351-355.

Digital Random Sequence Generation Algorithmand VLSI Implementation

  • Received Date: 2009-06-05
  • Rev Recd Date: 1900-01-01
  • Publish Date: 2010-04-05
  • A VLSI array synthesizing digital ran-
    dom sequence algorithm is proposed, and its Application-
    speci¯c integrated circuit (ASIC) design of the General
    random number generator (GRNG) which can generate
    digital random sequence with uniform distribution, expo-
    nential distribution, Rayleigh distribution and Gaussian
    distribution is introduced. In this algorithm, the Box-
    Muller equation is adopted for real-time generating ran-
    dom number using hardware, and one improved Taus-
    worthe sequence generating principle is proposed to speed
    up the generation and improve the signal quality. More-
    over, the pipelined Coordinate rotation digital computer
    (CORDIC) mapping algorithm is used to increases the
    throughput. The proposed GRNG is implemented with
    SMIC one-poly six-metal 0.18¹m CMOS technology. The
    ASIC core occupies 1:8 £ 1:8mm2 die area which generates
    16-bit or 32-bit samples up to 4¾, the peak throughput
    of the ASIC is 420 million samples per second, and the
    peak power dissipation, which includes the power of I/O,
    is 416mW in active mode, and 106mW in standby mode
    respectively in typical operation condition.
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