FU Yong, WANG Chi, CHEN Liguang, LAI Jinmei. A Full Coverage Test Method for Configurable Logic Blocks in FPGA[J]. Chinese Journal of Electronics, 2013, 22(3): 471-476.
Citation: FU Yong, WANG Chi, CHEN Liguang, LAI Jinmei. A Full Coverage Test Method for Configurable Logic Blocks in FPGA[J]. Chinese Journal of Electronics, 2013, 22(3): 471-476.

A Full Coverage Test Method for Configurable Logic Blocks in FPGA

Funds:  This work is supported by the National High Technology Research and Development Program of China (863 Program) (No.2012AA012001).
  • Received Date: 2012-04-01
  • Rev Recd Date: 2012-09-01
  • Publish Date: 2013-06-15
  • FPGA's configurability makes it difficult for FPGA's manufacturers to fully test it. In this paper, a full coverage test method for FPGA's Configurable logic blocks (CLBs) is proposed, through which all basic logics of FPGA's every CLB can be fully tested. Innovative test circuits are designed using FPGA's internal resources to build Iterative logic arrays (ILAs) for Look-up tables (LUTs), distributed random access memories, configurable registers and other logics. The programmable interconnects needed to connect CLBs in these test circuits are also repeatable, making the configuration process much easier and the test speed much faster. The test method is transplantable and independent of FPGA's array size, so it can be applied to the test of different FPGAs. Xilinx's Virtex FPGA is taken as an example to explain our method, where only 19 test configurations are needed to achieve 100% coverage for all CLBs. To evaluate the test method reliably and guide the process of test vectors generation, a fault simulator Turbofault is used to simulate FPGA's test coverage.
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  • M. Renovell, J.M. Portal, J. Figueras and Y. Zorian, “RAMbased FPGA's: A test approach for the configurable logic”, Proc. of the Design, Automation and Test in Europe, Paris, pp.82-88, 1998.
    S. Toutounchi and A. LAI, “FPGA test and coverage”, Proc. IEEE International Test Conference, Baltimore, MD, USA, pp.599-607, 2002.
    B. Dutton and C. Stroud, “Built-in self-test of configurable logic blocks in Virtex-5 FPGAs”, 41th Southeastern Symposium on System Theory, Tullahoma, TN, USA, pp.230-234, 2009.
    W.K. Huang, F.J. Meyer and F. Lombardi, “Multiple fault detection in logic resources of FPGAs”, Proc. Defect and Fault Tolerance in VLSI Systems, pp.248-253, 1997.
    Shyue-Kung Lu and Chung-Yang Chen, “Fault detection and fault diagnosis techniques for lookup table FPGAs”, Proc. of the 11th Asian Test Symposium, Guam, USA, pp.236-241, 2002.
    Zhiquan Zhang, Zhiping Wen, Lei Chen, Tao Zhou, Fan Zhang, “BIST approach for testing configurable logic and memory resources in FPGAs”, IEEE Asia Pacific Conf. on Circuits and systems, pp.1767-1770, 2008.
    S. Dhingra, “Built-in self-test of logic resources in field programmable gate arrays using partial reconfiguration”, Master's Thesis, Auburn University, USA, 2006.
    A. Cilardo, C. Logiego, A. Mazaaeo and N. Mazzocca, “Revisiting application-dependent test for FPGA devices”, 16th IEEE European Test Symposium, Trondheim, pp.213, 2011.
    A.W. Ruan, Y. Wang, K. Shi, Z.J. Zhu, Q. Wu, X. Han, Y.B. Liao, “SSOC HW/SW co-verification technology for application of FPGA test and diagnosis”, 2011 International conference on computational problem-solving, Chengdu, China, pp.1-6, 2011.
    “Virtex 2.5V FPGA complete data sheet”, Xilinx Inc., 2002.
    “7 series FPGAs configurable logic block”, Xilinx Inc., 2011.
    “Logic array blocks and adaptive logic modules in Stratix IV devices”, Altera Inc., 2011.
    “TurboFault datasheet”, SynTest Inc., 2007.
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