FU Yong, WANG Chi, CHEN Liguang, et al., “A Full Coverage Test Method for Configurable Logic Blocks in FPGA,” Chinese Journal of Electronics, vol. 22, no. 3, pp. 471-476, 2013,
Citation: FU Yong, WANG Chi, CHEN Liguang, et al., “A Full Coverage Test Method for Configurable Logic Blocks in FPGA,” Chinese Journal of Electronics, vol. 22, no. 3, pp. 471-476, 2013,

A Full Coverage Test Method for Configurable Logic Blocks in FPGA

Funds:  This work is supported by the National High Technology Research and Development Program of China (863 Program) (No.2012AA012001).
  • Received Date: 2012-04-01
  • Rev Recd Date: 2012-09-01
  • Publish Date: 2013-06-15
  • FPGA's configurability makes it difficult for FPGA's manufacturers to fully test it. In this paper, a full coverage test method for FPGA's Configurable logic blocks (CLBs) is proposed, through which all basic logics of FPGA's every CLB can be fully tested. Innovative test circuits are designed using FPGA's internal resources to build Iterative logic arrays (ILAs) for Look-up tables (LUTs), distributed random access memories, configurable registers and other logics. The programmable interconnects needed to connect CLBs in these test circuits are also repeatable, making the configuration process much easier and the test speed much faster. The test method is transplantable and independent of FPGA's array size, so it can be applied to the test of different FPGAs. Xilinx's Virtex FPGA is taken as an example to explain our method, where only 19 test configurations are needed to achieve 100% coverage for all CLBs. To evaluate the test method reliably and guide the process of test vectors generation, a fault simulator Turbofault is used to simulate FPGA's test coverage.
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