CHANG Yisong, WEI Jizeng, ZHAO Guoyu, GUO Wei, SUN Jizhou. A Novel Architecture of Special Arithmetic Function Unit for Area-Efficient Programmable Vertex Shader[J]. Chinese Journal of Electronics, 2013, 22(3): 483-488.
Citation: CHANG Yisong, WEI Jizeng, ZHAO Guoyu, GUO Wei, SUN Jizhou. A Novel Architecture of Special Arithmetic Function Unit for Area-Efficient Programmable Vertex Shader[J]. Chinese Journal of Electronics, 2013, 22(3): 483-488.

A Novel Architecture of Special Arithmetic Function Unit for Area-Efficient Programmable Vertex Shader

Funds:  This work is supported in part by the National Natural Science Foundation of China (No.61070136) and the Doctoral Fund of Ministry of Education of China (No.20100032110041, No.20110032120037).
  • Received Date: 2012-04-01
  • Rev Recd Date: 2012-11-01
  • Publish Date: 2013-06-15
  • A novel architecture of high precision, floating-point special Arithmetic function unit (SFU) for elementary transcendental functions is presented in this paper to provide area efficiency as well as high performance for programmable vertex shader. From the architecture point of view, the evaluation of quadratic approximation for special functions is performed by sharing the SIMD vector unit in shader architecture to minimize processing latency and to reduce area cost in SFU. An optimized minimax approach is proposed as well to obtain the finite-length and normalized quadratic coefficients for high precision. The experiment result shows that the proposed SFU can significantly reduce area cost and by adopting the proposed SFU, a vertex shader with Transport triggered architecture (TTA) can achieve 15.0% improvement on average in performance/area ratio for various shading benchmarks.
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  • D. Kim, K. Chung, L.S. Kim et al., “An SoC with 1.3 Gtexels/s 3-D graphics full pipeline for consumer applications”, IEEE Journal of Solid-Srate Circuits, Vol.41, No.1, pp.71-84, 2006.
    C.H. Yu, K. Chung, D. Kim, L.S. Kim, “An energy-efficient mobile vertex processor with multithrad expanded VLIW architecture and vertex caches”, IEEE Journal of Solid-State Circuits, Vol.42, No.10, pp.2257-2269, 2007.
    J.M. Muller, “Partially rounded small-order approximations for accurate, hardware-qriented, table-based methods”, IEEE Symp. on Computer Arithmetic (ARITH-16), Santiago de Compostela, Spain, pp.114-121, 2003.
    J.A. Pineiro et al., “High-speed function approximation using a minimax quadratic interpolator”, IEEE Transactions on Computers, Vol.54, No.3, pp.304-318, 2005.
    D.D. Caro, N. Petra, A.G.M. Strollo, “High-performance special function unit for programmable 3-D graphics processors”, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.56, No.9, pp.1968-1978, 2009.
    W. Cui and S. Wu, “A new implementation of dedicated circuit for CORDIC algorithm”, Chinese Journal of Electronics, Vol.18, No.1, pp.69-73, 2009.
    D. Kim and L.S. Kim, “A floating-point unit for 4D vector inner product with reduced latency”, IEEE Transactions on Computers, Vol.58, No.7, pp.890-901, 2009.
    K. Chung and L.S. Kim, “Area-efficient special function unit for mobile vertex processors”, IEE Electronics Letters, Vol.45, No.16, pp.826-827, 2009.
    J. Wei, Y. Chang, W. Guo, J. Sun, “An optimized TTA-like vertex shader datapath for embedded 3D graphics processing unit”, Proc. Int. Conf. Very Large Scale Integration (VLSISoC), Hong Kong, China, pp.188-191, 2011.
    Y. Chang, J. Wei, W. Guo, J. Sun, “A multi-functional dot product unit with simd architecture for embedded 3D graphics engine”, Proc. Midwest Symposium on Circuits and Systems (MWSCAS), Seoul, Korea, pp.1-4, 2011.
    W. Guo, J.Wei et al., “Hybrid system level modeling and implementation of configurable processor for SoC”, Chinese Journal of Electronics, Vol.19, No.2, pp.237-240, 2010.
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