Very-Low-Voltage and Cross-Submicron-Technology Passive Tag’s Logic Design

SHI Weiwei; CHOY Chiusing

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Article Navigation > Chinese Journal of Electronics > 2013 > 22(4): 661-665

SHI Weiwei and CHOY Chiusing, “Very-Low-Voltage and Cross-Submicron-Technology Passive Tag’s Logic Design,” Chinese Journal of Electronics, vol. 22, no. 4, pp. 661-665, 2013,

Citation:

SHI Weiwei and CHOY Chiusing, “Very-Low-Voltage and Cross-Submicron-Technology Passive Tag’s Logic Design,” Chinese Journal of Electronics, vol. 22, no. 4, pp. 661-665, 2013,

SHI Weiwei and CHOY Chiusing, “Very-Low-Voltage and Cross-Submicron-Technology Passive Tag’s Logic Design,” Chinese Journal of Electronics, vol. 22, no. 4, pp. 661-665, 2013,

Citation:

SHI Weiwei and CHOY Chiusing, “Very-Low-Voltage and Cross-Submicron-Technology Passive Tag’s Logic Design,” Chinese Journal of Electronics, vol. 22, no. 4, pp. 661-665, 2013,

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Very-Low-Voltage and Cross-Submicron-Technology Passive Tag’s Logic Design

SHI Weiwei¹,
CHOY Chiusing²

1.
College of Information Engineering, Shenzhen University and Shenzhen Key Laboratory of Modern Communication and Information Processing, Shenzhen 518000, China;
2.
Department of Electronic Engineering, Chinese University of Hong Kong, Hong Kong, China

Funds: This work is supported by the Open Fund of the Key Laboratory of Modern Communication and Information Processing, Shenzhen, and the Innovative Technology Commission (ITC) of Hong Kong (No.GHS/020/06, No.ITP/017/07LP).

Received Date: 2012-08-01
Rev Recd Date: 2012-11-01
Publish Date: 2013-09-25

Abstract

Abstract

A low-voltage wide-tolerance-range passive UHF RFID tag's baseband logic design is presented in this paper. Based on deep submicron CMOS technologies, the design utilizes tailored techniques to satisfy subthreshold operation: to deal with the specific timing and wide-rangevariation problems at very low power supply, and for the consideration of limited availability of RF power. Compensated addition is proposed for the PIE decoder, and poweraware scheme is applied to the entire logic part. Galoi Linear feedback shift register (LFSR) and one-hot counter are also applied t ofulfill critical timing requirements. Additionally, these techniques help to improve clock efficiency and reduce the frequency variation impact in low-voltage data link portions. Therefore the robustness in subthreshold operation is ensured. The logic design was fabricated in 180nm, 130nm and 90nm CMOS technologies respectively to verify the compatibility. In measurement the designs indicate competent subthreshold operation. The 90nm version can function at 0.33V.
- Low voltage,
- Subthreshold logic,
- Radi ofrequency identification (RFID)

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References(11)

References

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