Parameterized Integrated Power and Performance (PIPP) Model for Ultra High-Performance of TOPS level DSP

Amdahl's law is a simple and fundamental tool for understanding the evolution of performance as a function of parallelism. Following a recent trend on timing and power analysis of general purpose many-core chip using this law, we develop a novel PIP Panalytical model for evaluating the performance and power of hierarchical on-chip large-scale parallel architectures with the core number, super-node size, processing element number, and function unit number taken into consideration. We thereby investigate the influence of workload characteristics (Thread-level parallel TLP, Instruction-level parallel IL Pand Data-level parallel DLP) on resource allocation with the restriction of performance and power. The results provide some feasible options to design TOPS level DS Parchitecture as well as a theoretical basis for making the design more scalable.