Citation: | WANG Pengjun, ZHANG Yuejun, ZHANG Xuelong, “Design of Two-phase SABL Flip-flop for Resistant DPA Attacks,” Chinese Journal of Electronics, vol. 22, no. 4, pp. 833-837, 2013, |
P. Kocher, J. Jaffe, B. Jun, “Differential power analysis”, Advancesi n Cryptology (CRYPTO'99), California, USA, pp.388-406, 1999.
|
E. Prouff, T. Roche, “Attack on a higher-order masking of theA ES based on homographic functions”, Lecture Notes in Computer Science, Vol.6498, No.2010, pp.262-281, 2010.
|
A. Moradi, O. Mischke, T. Eisenbarth, “Correlation-enhancedp ower analysis collision attack”, Lecture Notes in Computer Science, Vol.6225, No.2010, pp.125-139, 2010.
|
A. Bogdanov, I. Kizhvatov, “Beyond the limits of DPA: Combineds ide-channel collision attacks”, IEEE Transactions on Computers, Vol.61, No.8, pp.1153-1164, 2012.
|
S. Mangard, E. Oswald, T. Popp, Power Analysis Attacks: Revealingt he Secrets of Smart Cards, In: Springer-Verlag, Austria,pp.1-306, 2007.
|
J.A. Ambrose, R.G. Ragel, S. Parameswaran, A. Ignjatovic,“Multiprocessor information concealment architecture to preventp ower analysis-based side channel attacks”, Computers &D igital Techniques, IET, Vol.5, No.1, pp.1-15, 2011.
|
J.W. Lee, J.H. Hsiao, H.C. Chang, C.Y. Lee, “An efficient DPAc ountermeasure with randomized montgomery operations forD F-EC Cprocessor”, IEEE Transactions on Circuits and SystemsI I: Express Briefs, Vol.59, No.5, pp.287-291, 2012.
|
P.C. Liu, H.C. Chang, C.Y. Lee, “A true random-based differentialp ower analysis countermeasure circuit for an AES engine”,I EEE Transactions on Circuits and Systems II: Express Briefs,Vol.59, No.2, pp.103-107, 2012.
|
M. Bucci, L. Giancane, R. Luzzi, G. Scotti, A. Trifiletti, “Delaybasedd ual-rail precharge logic”, IEEE Transactions on VeryL arge Scale Integration (VLSI) Systems, Vol.19, No.7, pp.1147-1 153, 2010.
|
K. Tiri, M. Akmal, I. Verbauwhede, “A dynamic and differential CMOS logic with signal independent power consumptiont o withstand differential power analysis on smart cards”, Proceedings of the 28th European Solid-State Circuits Conference,F irenze, Italie, pp.403-406, 2002.
|
M. Bucci, L. Giancane, R. Luzzi, A. Trifiletti, “Three-phased ual-rail pre-charge logic”, Lecture Notes in Computer Science,Vol.4249, No.2006, pp.232-241, 2006.
|
T. Popp, S. Mangard, “Masked dual-rail pre-charge logic: DPAresistancew ithout routing constraints”, Lecture Notes in ComputerS cience, Vol.3659, No.2005, pp.172-186, 2005.
|
K. Tiri, I. Verbauwhede, “A logic level design methodology fora secure DPA resistant ASI Cor FPGA implementation”, ProceedingsD esign, Automation and Test in Europe Conference and Exhibition, Washington, USA, pp.246-251, 2004.
|
F. Burns, A. Bystrov, A. Koelmans, A. Yakovlev, “Design ands ecurity evaluation of balanced 1-of-n circuits”, Computers &Digital Techniques, IET, Vol.6, No.2, pp.125-135, 2012.
|