Design of Two-phase SABL Flip-flop for Resistant DPA Attacks

Differential power analysis (DPA) poses a great threat to cipher security circuit since it exploits the dependency between the processed data and the power consumption. Two-phase Sense amplifier based logic (Twophase SABL) suitable to DPA resistant logic style has been introduced under unbalanced load conditions. The proposed logic obtains constant energy consumption per clock cycle with pre-charge and evaluation phases. In this paper, Two-phase SABL cell and flip-flop are designed and simulated to confirm the energy balancing characteristic. Using TSM C0.13μm CMOS technique, simulation results show that the power consumption fluctuations in the flip-flop is decreased by 15.1% under unbalanced condition and the area is reduced by 38.4%.