WANG Pengjun, ZHANG Yuejun, ZHANG Xuelong. Design of Two-phase SABL Flip-flop for Resistant DPA Attacks[J]. Chinese Journal of Electronics, 2013, 22(4): 833-837.
Citation: WANG Pengjun, ZHANG Yuejun, ZHANG Xuelong. Design of Two-phase SABL Flip-flop for Resistant DPA Attacks[J]. Chinese Journal of Electronics, 2013, 22(4): 833-837.

Design of Two-phase SABL Flip-flop for Resistant DPA Attacks

Funds:  This work is supported by the National Natural Science Foundation of China (No.61274132, No.61076032);Research Fund for the Doctoral Program of Higher Education of China (No.20113305110005);the Key Project of Zhejiang Provincial Natural Science Foundation of China (No.Z1111219);the K.C. Wong Magna Fund in Ningbo University, China;the Excellent Doctoral Dissertation Foundation of Ningbo University (No.PY20100003).
More Information
  • Corresponding author: WANG Pengjun, ZHANG Yuejun, ZHANG Xuelong
  • Received Date: 2012-11-01
  • Rev Recd Date: 2013-04-01
  • Publish Date: 2013-09-25
  • Differential power analysis (DPA) poses a great threat to cipher security circuit since it exploits the dependency between the processed data and the power consumption. Two-phase Sense amplifier based logic (Twophase SABL) suitable to DPA resistant logic style has been introduced under unbalanced load conditions. The proposed logic obtains constant energy consumption per clock cycle with pre-charge and evaluation phases. In this paper, Two-phase SABL cell and flip-flop are designed and simulated to confirm the energy balancing characteristic. Using TSM C0.13μm CMOS technique, simulation results show that the power consumption fluctuations in the flip-flop is decreased by 15.1% under unbalanced condition and the area is reduced by 38.4%.
  • loading
  • P. Kocher, J. Jaffe, B. Jun, “Differential power analysis”, Advancesi n Cryptology (CRYPTO'99), California, USA, pp.388-406, 1999.
    E. Prouff, T. Roche, “Attack on a higher-order masking of theA ES based on homographic functions”, Lecture Notes in Computer Science, Vol.6498, No.2010, pp.262-281, 2010.
    A. Moradi, O. Mischke, T. Eisenbarth, “Correlation-enhancedp ower analysis collision attack”, Lecture Notes in Computer Science, Vol.6225, No.2010, pp.125-139, 2010.
    A. Bogdanov, I. Kizhvatov, “Beyond the limits of DPA: Combineds ide-channel collision attacks”, IEEE Transactions on Computers, Vol.61, No.8, pp.1153-1164, 2012.
    S. Mangard, E. Oswald, T. Popp, Power Analysis Attacks: Revealingt he Secrets of Smart Cards, In: Springer-Verlag, Austria,pp.1-306, 2007.
    J.A. Ambrose, R.G. Ragel, S. Parameswaran, A. Ignjatovic,“Multiprocessor information concealment architecture to preventp ower analysis-based side channel attacks”, Computers &D igital Techniques, IET, Vol.5, No.1, pp.1-15, 2011.
    J.W. Lee, J.H. Hsiao, H.C. Chang, C.Y. Lee, “An efficient DPAc ountermeasure with randomized montgomery operations forD F-EC Cprocessor”, IEEE Transactions on Circuits and SystemsI I: Express Briefs, Vol.59, No.5, pp.287-291, 2012.
    P.C. Liu, H.C. Chang, C.Y. Lee, “A true random-based differentialp ower analysis countermeasure circuit for an AES engine”,I EEE Transactions on Circuits and Systems II: Express Briefs,Vol.59, No.2, pp.103-107, 2012.
    M. Bucci, L. Giancane, R. Luzzi, G. Scotti, A. Trifiletti, “Delaybasedd ual-rail precharge logic”, IEEE Transactions on VeryL arge Scale Integration (VLSI) Systems, Vol.19, No.7, pp.1147-1 153, 2010.
    K. Tiri, M. Akmal, I. Verbauwhede, “A dynamic and differential CMOS logic with signal independent power consumptiont o withstand differential power analysis on smart cards”, Proceedings of the 28th European Solid-State Circuits Conference,F irenze, Italie, pp.403-406, 2002.
    M. Bucci, L. Giancane, R. Luzzi, A. Trifiletti, “Three-phased ual-rail pre-charge logic”, Lecture Notes in Computer Science,Vol.4249, No.2006, pp.232-241, 2006.
    T. Popp, S. Mangard, “Masked dual-rail pre-charge logic: DPAresistancew ithout routing constraints”, Lecture Notes in ComputerS cience, Vol.3659, No.2005, pp.172-186, 2005.
    K. Tiri, I. Verbauwhede, “A logic level design methodology fora secure DPA resistant ASI Cor FPGA implementation”, ProceedingsD esign, Automation and Test in Europe Conference and Exhibition, Washington, USA, pp.246-251, 2004.
    F. Burns, A. Bystrov, A. Koelmans, A. Yakovlev, “Design ands ecurity evaluation of balanced 1-of-n circuits”, Computers &Digital Techniques, IET, Vol.6, No.2, pp.125-135, 2012.
  • 加载中

Catalog

    通讯作者: 陈斌, bchen63@163.com
    • 1. 

      沈阳化工大学材料科学与工程学院 沈阳 110142

    1. 本站搜索
    2. 百度学术搜索
    3. 万方数据库搜索
    4. CNKI搜索

    Article Metrics

    Article views (275) PDF downloads(1100) Cited by()
    Proportional views
    Related

    /

    DownLoad:  Full-Size Img  PowerPoint
    Return
    Return