Citation: | FANG Juan, WANG Jing, LI Chengyan, et al., “Partition-Based Cache Replacement to Manage Shared L2 Caches,” Chinese Journal of Electronics, vol. 23, no. 3, pp. 464-467, 2014, |
L. A. Belady, "A study of replacement algorithms for virtual storage computers", IBM Systems Journal, Vol.5, No.2, pp.78-101, 1966.
|
C. Zhang, B. Xue, "Divide-and-Conquer: A bubble replacement for low level caches", Proc. of ACM International Conference on Supercomputing, Yorktown Heights, NY, USA, pp.80-89, 2009.
|
M. K. Qureshi, A. Jaleel, Y. N. Patt, et al., "Adaptive insertion policies for high-performance caching", Proc. of IEEE International Symposium on Computer Architecture, San Diego, CA, USA, pp.381-391, 2007.
|
M. K. Qureshi, Y. N. Patt. "Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches", Proc. of IEEE/ACM International Symposium on Microarchitecture, Orlando, Florida, USA, pp.423-432, 2006.
|
H. Dybdahl, "An LRU-based replacement algorithm augmented with frequency of access in shared chip multiprocessor caches", ACM SIGARCH Computer Architecture News, Vol.35, No.4, pp.45-52, 2007.
|
S. Jiang, X. Zhang, "LIRS: An efficient low inter-reference recency set replacement policy to improve buffer cache performance", Proc. of ACM SIGMETRICS Conference on Measurements and Modeling of Computer Systems, Marina Del Rey, California, USA, pp.31-42, 2002.
|
M. K.Qureshi, D. N. Lynch, O. Mutlu, et al., "A case for MLPaware cache replacement". Proc. of IEEE International Symposium on Computer Architecture, Boston, MA, USA, pp.167-178, 2006.
|
R. Subramanian, Y. Smaragdakis, G. H. Loh, "Adaptive caches: Effective shaping of cache behavior to workloads", Proc. of IEEE/ACM International Symposium on Microarchitecture, Orlando, Florida, USA, pp.385-396, 2006.
|
D. Sanchez, C. Kozyrakis, "Vantage: Scalable and efficient finegrain cache partitioning", Proc. IEEE International Symposium on Computer Architecture, San Jose, CA, USA, pp.57-68, 2011.
|
S. Srikantaiah, M. Kandemir, Q. Wang, "SHARP control: Controlled shared cache management in chip multiprocessors", Proc. of IEEE/ACM International Symposium on Microarchitecture, New York, USA, pp.517-528, 2009.
|
Y. Xie, G. H. Loh, "PIPP: Promotion/insertion pseudopartitioning of multi-core shared caches", Proc. of IEEE International Symposium on Computer Architecture, Austin, TX, USA, pp.174-183, 2009.
|
M. Kharbutli, Y. Solihin, "Counter-based cache replacement and bypassing algorithms", IEEE Transactions on Computers, Vol.57, No.4, pp.433-447, 2008.
|
P. Magnusson, M. Christensson, J. Eskilson, et al., "Simics: A full system simulation platform", IEEE Computer, Vol.35, No.2, pp.50-58, 2002.
|
M. M. Martin, D. J. Sorin, B. M. Beckmann, et al., "Multifacet's General execution-driven multiprocessor simulator (GEMS) toolset", ACM SIGARCH Computer Architecture News, Vol.33, No.4, pp.92-99, 2005.
|
V. Aslot, M. Domeika, R. Eigenmann, et al., "SpecOMP: A new benchmark suite for measuring parallel computer performance", Lecture Notes in Computer Science, Vol.2104, pp.1-10, 2001.
|