Citation: | YIN Shouyi, ZHANG Zhen, HU Yang, et al., “Mixed-Level Modeling Methodology for Network-on-Chip Architecture Exploration,” Chinese Journal of Electronics, vol. 23, no. 3, pp. 468-473, 2014, |
Initiative, Open SystemC. "OSCI TLM-2.0 user manual", http://www.systemc.org, 2008-6-9.
|
Adve, Sarita V., Kourosh Gharachorloo, "Shared memory consistency models: A tutorial.", Computer, Vol.29, No.12, pp.66-76, 1996.
|
Fazzino F., M. Palesi, D. Patti, "Noxim: Network-on-chip simulator", http://sourceforge. net/projects/noxim, 2013-10-26.
|
Jain, Lavina, et al., "NIRGAM: A simulator for NoC interconnect routing and application modeling", Design, Automation and Test in Europe Conference, pp.16-20, 2007.
|
Amit Kumar, et al., "A system-level perspective for efficient NoC design", IEEE International Symposium on Parallel and Distributed Processing, pp.1-5, 2008.
|
J. E. Miller, H. Kasture, G. Kurian, C. Gruenwald, et al., "Graphite: A distributed parallel simulator for multicores", International Symposium on High Performance Computer Architecture, pp.1-12, 2010.
|
Ren Pengju, Mieszko Lis, Myong Hyon Cho, et al., "HORNET: A cycle-level multicore simulator", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.31, No.6, pp.890-903, 2012.
|
Zolghadr, Mahdy, Koosha Mirhosseini, et al., "GPU-based NoC simulator", IEEE/ACM International Conference on Formal Methods and Models for Codesign, pp.83-88, 2011.
|
Pellauer Michael, et al., "A-port networks: Preserving the timed behavior of synchronous systems for modeling on FPGAs", ACM Transactions on Reconfigurable Technology and Systems, Vol.2, No.3, pp.1-26, 2009.
|
Banerjee, Nilanjan, Praveen Vellanki, et al., "A power and performance model for network-on-chip architectures", Design, Automation and Test in Europe Conference, pp.1250-1255, 2004.
|
J.Emer, P.AHuja, E.Borch, et al., "Asim: A performance model", Computer, Vol.35, No.2, pp.68-76, 2002.
|