Mixed-Level Modeling Methodology for Network-on-Chip Architecture Exploration

As Network on chip (NoC) architecture develops as an solution of interconnection in System on chip (SoC) designs, a detailed and flexible interconnection network model integrated in a full system evaluation framework becomes necessary. In this paper, we first present a mixed abstraction level modeling methodology for the performance evaluation of NoC architecture. Then based on our mixed level modeling methodology, we develop a full system mixed-level NoC evaluation and verification platform. Aiming to explore the details of the performance evaluation and hardware verification of interconnection part, we build NoC router at cycle-accurate, bus cycle level and build SoC peripherals at approximately time, bus phase transaction level which intend to gain higher simulation speed, and lower step to relative development of software. The experimental results show that the mixedlevel NoC evaluation platform can achieve both detailed architecture exploration and fast simulation speed.