WANG Yongqing, MA Yuanxing, LIU Donglei, et al., “An SEU-Tolerant Approach for Space-Borne Viterbi Decoders,” Chinese Journal of Electronics, vol. 23, no. 4, pp. 857-861, 2014,
Citation: WANG Yongqing, MA Yuanxing, LIU Donglei, et al., “An SEU-Tolerant Approach for Space-Borne Viterbi Decoders,” Chinese Journal of Electronics, vol. 23, no. 4, pp. 857-861, 2014,

An SEU-Tolerant Approach for Space-Borne Viterbi Decoders

Funds:  This work is supported by the National High Technology Research and Development Program of China (863 Program) (No.2012AA1406).
  • Received Date: 2013-04-01
  • Rev Recd Date: 2014-05-01
  • Publish Date: 2014-10-05
  • In the space environment, Viterbi decoder implemented on SRAM-based FPGA is sensitive to Single event upsets (SEUs), which may lead to functional failure of the decoder. Conventional SEU mitigation techniques like modular redundancy could not exploit the characters of Viterbi decoders, therefore could not provide optimized SEU tolerance when the device resource utilization cost is a constraint. Leveraging the properties of the decoding algorithm, three effective mitigation techniques are adopted, including structure optimization, Error detection and correction (EDAC) for Block RAM (BRAM) protection, and Partial triple-modular redundancy (PTMR), which are applied to the modules of the decoder in accordance with their characteristics. Analysis of effectiveness shows that compared with unmitigated design, the SEU induced failure rate in the proposed SEU tolerant decoder can be reduced to 1/4 at the cost of 61.1% extra resource utilization.
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  • Wang Jianxin and Yu Guizhi, Study on inlplementation of traceback algorithm in Viterbi decoders, Journal of Electronics & Information Technology, Vol.29, No.2, pp.278-282, 2007. (in Chinese)
    Edmonds and D. Larry, SRAM FPGA reliability analysis for harsh radiation environments, IEEE Transactions on Nuclear Science, Vol.56, No.6, pp.3519-3526, 2009.
    Gong Jian and Yang Mengfei, An FPGA bit-stream read back and reconfiguration based hardware fault tolerance method for space applications, Aerospace Control and Application, Vol.38, No.1, pp.34-39, 2012. (in Chinese)
    Ma Yin, SEU-tolerant design of SRAM FPGA for space use, Spacecraft Environment Engineering, Vol.28, No.6, pp.551-555, 2011. (in Chinese)
    Yang Wenlong, Wang Lingli and Zhou Xuegong, CRC circuit design for SRAM-based FPGA configuration bit correction, Proc. of International Conference on Solid-state and Integrated Circuit Technology, Shanghai, pp.1660-1664, 2010.
    L. Sterpone, M. Violante, A. Panariti, et al., Layout-aware multi-cell upsets effects analysis on TMR circuits implemented on SRAM-based FPGAs, IEEE Transactions on Nuclear Science, Vol.58, No.5, pp.2325-2332, 2011.
    L. Sterpone and M. Violante, Analysis of the robustness of the TMR architecture in SRAM-based FPGAs, IEEE Transactions on Nuclear Science, Vol.52, No.5, pp.1545-1549, 2005.
    Dang Wei, Sun Hui-zhong, Li Rui-ying, M. Ceschia, et al., Research on reliability assurance of COTS components in space application, Acta Electronica Sinica, Vol.37, No.11, pp.2589-2594, 2009. (in Chinese)
    F.L. Kastensmidt and R. Reis, Fault tolerance in programmable circuits, Radiation Effects on Embedded Systems, The Netherlands, pp.161-182, 2010.
    M. Violante, L. Sterpone, M. Ceschia, et al., Simulation-based analysis of SEU effects in SRAM-based FPGAs, IEEE Transactions on Nuclear Science, Vol.51, No.6, pp.3354-3359, 2004.
    Yao Zhibin, Fan Ruyu, Guo Hongxia, et al., Acquisition and classification of static single-event upset cross section for SRAM-based FPGAs, High Power Laser and Particle Beams, Vol.23, No.3, pp.811-816, 2011. (in Chinese)
    Xilinx Inc., Virtex-II Platform FPGA User Guide, USA, pp.10-50, 2007.
    G. Asadi and M.B. Tahoori, Soft error rate estimation and mitigationfor SRAM-based FPGAs, ACM/SIGDA International Symposiumon Field-Programmalbe Gate Arrays, Seoul, pp.2714-2726, 2005.
    K.S. Morgan, D.L. McMurtrey, B.H. Pratt, et al., A comparison of TMR with alternative fault-tolerant design techniques for FPGAs, IEEE Transactions on Nuclear Science, Vol.54, No.6, pp.2065-2072, 2007.
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