PAN Min, FENG Jun. Design of a Low-Power 20Gb/s 1:4 Demultiplexer in 0.18μm CMOS[J]. Chinese Journal of Electronics, 2015, 24(1): 71-75.
Citation: PAN Min, FENG Jun. Design of a Low-Power 20Gb/s 1:4 Demultiplexer in 0.18μm CMOS[J]. Chinese Journal of Electronics, 2015, 24(1): 71-75.

Design of a Low-Power 20Gb/s 1:4 Demultiplexer in 0.18μm CMOS

Funds:  This work is supported by the National High Technology Research and Development Program of China (863 Program) (No.2011AA10305).
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  • Corresponding author: FENG Jun was born in Huai'an city, Jiangsu Province, China, in 1953. She is a professor and doctoral supervisor in School of Information Science and Engineering of Southeast University, China. Her research work focuses on the design of high-speed optical communication IC. (E-mail: fengjun@seu.edu.cn)
  • Received Date: 2013-08-01
  • Rev Recd Date: 2013-12-01
  • Publish Date: 2015-01-10
  • A low-power multi-phase clock 20Gb/s 1:4 Demultiplexer (DEMUX) without inductors is designed in 0.18μm Complementary metal oxide semiconductor (CMOS) process. The 1:4 DEMUX includes two 1:2 DEMUX cells, one 1/2 frequency divider cell, some data and clock buffers. A dynamic CMOS logic latch is used in the 1:2 DEMUX cell and a single clock dynamic-loading latch is used in the 1/2 frequency divider cell. These two kinds of logical structures not only reduce power dissipation and area, but also have an output rail-to-rail level. The rail-to-rail level can offer high noise margin and implement seamless connection without logic level conversion in system integration. The test results show that when the data rate of the input pseudorandom is 20Gb/s and the sequence length is 231-1, this 1:4 DEMUX can work well at a supply voltage of 2V. The output swing is 450mV with external 50 Ohm load and the die size is 0.475× 0.475 mm2. The chip power dissipation is 86mW, when four pads connect with a four-channel oscillograph.
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