A Process-Compatible Self-biased PLL with Flexible Reference of 0.001~1.2GHz and Output of 0.016~3.5GHz

This paper presents a charge pump phase-locked loop (PLL) with an input range of 1 MHz to 1.2 GHz and an output frequency range of 16 MHz to 3.5 GHz. The proposed design employs global self-bias and bandwidth-adaptive techniques, eliminating the need for large bias circuits and reducing power consumption. The circuit is implemented using both planar technology and FinFET technology, demonstrating high stability and compatibility in both system-synchronous and source-synchronous applications through experimental validation.