A Single-Channel 10bit 500MS/s TD-ADC with a Randomization Technique for the GRO-based TDC

This paper presents a single-channel 10-bit time-domain analog-to-digital converter (ADC) operating at 500 MS/s. In order to solve the contradiction between the input dynamic range and the conversion linearity, this paper proposes a new voltage-to-time converter (VTC) structure with a large input dynamic range as well as a high linearity current source, which improves the linearity of the VTC and increases the input signal swing at the same time. A novel time-to-digital converter (TDC) structure based on a gated ring oscillator (GRO) combining coarse and fine quantization is proposed, which effectively reduces the chip area and the overall power consumption. Meanwhile, in order to reduce the GRO quantization phase shift caused by non-ideal factors, this design proposes a randomization technique for the GRO, which effectively improves the linearity. Finally, the prototype ADC was fabricated using a 28-nm CMOS process, occupying a core area of 0.0053 mm2. After the randomization technique turned on, demonstrated a SNDR of 52.54 dB and a SFDR of 67.51 dB at a sampling rate of 500 MS/s with a Nyquist input frequency, resulting in an effective number of bits (ENOB) of 8.43. It operated at a 1-V sup-ply, consuming 3.97 mW, and achieved a Walden figure of merit (FoM) of 23 fJ/conversion-step.