On-Chip Generating FPGA Test Configuration Bitstreams to Reduce Manufacturing Test Time

WANG Fei; WANG Da; YANG Haigang; XIE Xianghui; FAN Dongrui

doi:10.1049/cje.2016.01.010

Volume 25 Issue 1

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WANG Fei, WANG Da, YANG Haigang, et al., “On-Chip Generating FPGA Test Configuration Bitstreams to Reduce Manufacturing Test Time,” Chinese Journal of Electronics, vol. 25, no. 1, pp. 64-70, 2016, doi: 10.1049/cje.2016.01.010

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WANG Fei, WANG Da, YANG Haigang, et al., “On-Chip Generating FPGA Test Configuration Bitstreams to Reduce Manufacturing Test Time,” Chinese Journal of Electronics, vol. 25, no. 1, pp. 64-70, 2016, doi: 10.1049/cje.2016.01.010

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On-Chip Generating FPGA Test Configuration Bitstreams to Reduce Manufacturing Test Time

doi: 10.1049/cje.2016.01.010

1.
System on Programmable Chip Research Department, IE, CAS, Beijing 100190, China;
2.
State Key Laboratory of Computer Architecture, ICT, CAS, Beijing 100190, China;
3.
State Key Laboratory of Mathematical Engineering and Advanced Computing, Wuxi 214125, China

Funds: This work is supported by the National Basic Research Program of China (973 Program) (No.2011CB302501), the National High Technology Research and Development Program of China (863 Program) (No.2015AA01A301), the National Science Foundation of China (No.61204047, No.61204045, No.61332009), the Major Project of China (No.2013ZX0102-8001-001-001), and Beijing Natural Science Foundation (No.4143060).

Received Date: 2014-02-13
Rev Recd Date: 2015-05-25
Publish Date: 2016-01-10

Abstract

Abstract

Statistics shows that over 95% of FPGA manufacturing test time is spent on loading test configuration bitstreams. Reducing the test time that spent on loading test configuration bitstreams could significantly reduce FPGA test time. A new approach which can significantly reduce the FPGA test time is presented. Experimental results show that the proposed technique can at least reduce the configuration loading time by 96%, while getting 100% test coverage with less than 1.2% hardware overhead.
- FPGA test,
- Test configuration bitstream,
- Design-for-testability

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References(20)

References

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