WANG Fei, WANG Da, YANG Haigang, XIE Xianghui, FAN Dongrui. On-Chip Generating FPGA Test Configuration Bitstreams to Reduce Manufacturing Test Time[J]. Chinese Journal of Electronics, 2016, 25(1): 64-70. DOI: 10.1049/cje.2016.01.010
Citation: WANG Fei, WANG Da, YANG Haigang, XIE Xianghui, FAN Dongrui. On-Chip Generating FPGA Test Configuration Bitstreams to Reduce Manufacturing Test Time[J]. Chinese Journal of Electronics, 2016, 25(1): 64-70. DOI: 10.1049/cje.2016.01.010

On-Chip Generating FPGA Test Configuration Bitstreams to Reduce Manufacturing Test Time

  • Statistics shows that over 95% of FPGA manufacturing test time is spent on loading test configuration bitstreams. Reducing the test time that spent on loading test configuration bitstreams could significantly reduce FPGA test time. A new approach which can significantly reduce the FPGA test time is presented. Experimental results show that the proposed technique can at least reduce the configuration loading time by 96%, while getting 100% test coverage with less than 1.2% hardware overhead.
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