LIU Qiang, GAO Ming, ZHANG Tao, ZHANG Qijun. Feedforward Neural Network Models for FPGA Routing Channel Width Estimation[J]. Chinese Journal of Electronics, 2016, 25(1): 71-76. doi: 10.1049/cje.2016.01.011
Citation: LIU Qiang, GAO Ming, ZHANG Tao, ZHANG Qijun. Feedforward Neural Network Models for FPGA Routing Channel Width Estimation[J]. Chinese Journal of Electronics, 2016, 25(1): 71-76. doi: 10.1049/cje.2016.01.011

Feedforward Neural Network Models for FPGA Routing Channel Width Estimation

doi: 10.1049/cje.2016.01.011
Funds:  This work is supported by the National Natural Science Foundation of China (No.61204022, No.61350009), the Natural Science Foundation of Tianjin (No.12JCYBJC30700), and the Scientific Research Foundation for the Returned Overseas Chinese Scholars, State Education Ministry.
More Information
  • Corresponding author: ZHANG Tao (corresponding author) received the Ph.D. degree in signal and information processing at Tianjin University in 2004. He is currently an associated professor in School of Electronic Information Engineering at Tianjin University. His current research interests include signal processing and VLSI system design. (Email: todd@tju.edu.cn)
  • Received Date: 2014-01-16
  • Rev Recd Date: 2014-07-03
  • Publish Date: 2016-01-10
  • Since interconnects play the increasingly important role in delay and area of the Field-programmable gate array (FPGA) implementations, routing architecture design has become the focus of much work related to FPGA architecture development. This paper leverages feedforward neural networks to derive accurate models of the routing channel width in homogeneous FPGA architecture with two advanced intelligence learning techniques: Gradient-based learning algorithm (GLA) and Extreme learning machine (ELM). The resultant models can be used in the early stages of FPGA architecture development to facilitate fast design space exploration which is difficult to achieve in the traditional experiment-based method. The proposed models are evaluated by comparing the estimated channel widths to the real values generated from a CAD tool VTR over IWLS2005 benchmark circuits. Results show that the GLA model achieves the estimation accuracy 3.98% and the ELM model has the accuracy 3.91%, which show significant improvement over existing estimation approaches.
  • loading
  • V. Betz, J. Rose and A. Marquardt, Architecture and CAD for Deep-submicron FPGAs, Kluwer Academic Publishers, Norwell, MA, USA, 1999.
    J. Das, A. Lam, S.J.E. Wilton, et al., “An analytical model relating FPGA architecture to logic density and depth”, IEEE Trans. VLSI, Vol.19, No.12, pp.2229-2242, 2011.
    A.M. Smith, G.A. Constantinides and P.Y.K. Cheung, “FPGA architecture optimization using geometric programming”, IEEE Trans. CAD, Vol.29, No.8, pp.1163-1176, 2010.
    W.M. Fang and J. Rose, “Modeling routing demand for earlystage FPGA architecture development”, Proc. of ACM/SIGDA Symposium on Field Programmable Gate Arrays, Monterey, California, USA, pp.139-148, 2008.
    S. Balachandran and D. Bhatia, “A priori wirelength and interconnect estimation based on circuit characteristics”, IEEE Trans. CAD, Vol.24, No.7, pp.1054-1065, 2005.
    P. Kannan and D. Bhatia, “Interconnect estimation for FPGAs”, IEEE Trans. CAD, Vol.25, No.8, pp.1523-1534, 2006.
    J. Lou, S. Thakur, S. Krishnamoorthy and H.S. Sheng, “Estimating routing congestion using probabilistic analysis”, IEEE Trans. CAD, Vol.21, No.1, pp.32-41, 2002.
    C.L.E. Cheng, “Risa: Accurate and efficient placement routability modeling”, Proc. of IEEE/ACM International Conference on Computer-Aided Design, pp.690-695, 1994.
    X. Yang, R. Kastner and M. Sarrafzadeh, “Congestion estimation during top-down placement”, IEEE Trans. CAD, Vol.21, No.1, pp.32-41, 2002.
    P.K. Chan, M.D.F. Schlag and J.Y. Zien, “On routability prediction for field-programmable gate arrays”, Proc. of Conference on Design Automation, pp.326-330, 1993.
    Q. Liu and J. Ma and Q. Zhang, “Neural network based preplacement wirelength estimation”, Proc. of International Conference on Field-Programmable Technology, pp.16-22, 2012.
    Q. Zhang, K.C. Gupta and V.K. Devabhaktuni, “Artificial neural networks for RF and microwave design — from theory to practice”, IEEE Trans. Microwave Theory Tech., Vol.51, No.4, pp.1339-1350, 2003.
    G.B. Huang, Q.Y. Zhu and C.K. Siew, “Extreme learning machine: Theory and applications”, Neurocomputing, Vol.70, pp.489-501, 2005.
    C. Albrecht, “IWLS 2005 benchmarks”, available at http:// iwls.org/iwls2005/benchmarks.html, 2005.
    J. Rose, J. Luu, C.W. Yu, O. Densmore, J. Goeders, A. Somerville, K.B. Kent, P. Jamieson and J. Anderson, “The VTR project: Architecture and CAD for FPGAs from verilog to routing”, Proc. of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pp.77-86, 2012.
    Q. Zhang, “NeuroModeler”, available at http://www.doe.carleton. ca/~qjz/, 2014.
    A.M. Smith, S.J.E. Wilton and J. Das, “Wirelength modeling for homogeneous and heterogeneous FPGA architectural development”, Proc. of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pp.181-190, 2009.
  • 加载中

Catalog

    通讯作者: 陈斌, bchen63@163.com
    • 1. 

      沈阳化工大学材料科学与工程学院 沈阳 110142

    1. 本站搜索
    2. 百度学术搜索
    3. 万方数据库搜索
    4. CNKI搜索

    Article Metrics

    Article views (218) PDF downloads(870) Cited by()
    Proportional views
    Related

    /

    DownLoad:  Full-Size Img  PowerPoint
    Return
    Return