Feedforward Neural Network Models for FPGA Routing Channel Width Estimation

LIU Qiang; GAO Ming; ZHANG Tao; ZHANG Qijun

doi:10.1049/cje.2016.01.011

Volume 25 Issue 1

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LIU Qiang, GAO Ming, ZHANG Tao, et al., “Feedforward Neural Network Models for FPGA Routing Channel Width Estimation,” Chinese Journal of Electronics, vol. 25, no. 1, pp. 71-76, 2016, doi: 10.1049/cje.2016.01.011

Citation:

LIU Qiang, GAO Ming, ZHANG Tao, et al., “Feedforward Neural Network Models for FPGA Routing Channel Width Estimation,” Chinese Journal of Electronics, vol. 25, no. 1, pp. 71-76, 2016, doi: 10.1049/cje.2016.01.011

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Feedforward Neural Network Models for FPGA Routing Channel Width Estimation

doi: 10.1049/cje.2016.01.011

School of Electronic Information Engineering, Tianjin University, Tianjin 300072, China

Funds: This work is supported by the National Natural Science Foundation of China (No.61204022, No.61350009), the Natural Science Foundation of Tianjin (No.12JCYBJC30700), and the Scientific Research Foundation for the Returned Overseas Chinese Scholars, State Education Ministry.

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Corresponding author: ZHANG Tao (corresponding author) received the Ph.D. degree in signal and information processing at Tianjin University in 2004. He is currently an associated professor in School of Electronic Information Engineering at Tianjin University. His current research interests include signal processing and VLSI system design. (Email: todd@tju.edu.cn)
Received Date: 2014-01-16
Rev Recd Date: 2014-07-03
Publish Date: 2016-01-10

Abstract

Abstract

Since interconnects play the increasingly important role in delay and area of the Field-programmable gate array (FPGA) implementations, routing architecture design has become the focus of much work related to FPGA architecture development. This paper leverages feedforward neural networks to derive accurate models of the routing channel width in homogeneous FPGA architecture with two advanced intelligence learning techniques: Gradient-based learning algorithm (GLA) and Extreme learning machine (ELM). The resultant models can be used in the early stages of FPGA architecture development to facilitate fast design space exploration which is difficult to achieve in the traditional experiment-based method. The proposed models are evaluated by comparing the estimated channel widths to the real values generated from a CAD tool VTR over IWLS2005 benchmark circuits. Results show that the GLA model achieves the estimation accuracy 3.98% and the ELM model has the accuracy 3.91%, which show significant improvement over existing estimation approaches.

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References(17)

References

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