Ultra-thin Body Buried In<sub>0.35</sub>Ga<sub>0.65</sub>As Channel MOSFETs with Extremely Low Off-current on Si Substrates

WANG Bo; DING Peng; FENG Ruize; WANG Yanfu; LIU Xiaoyu; SUN Tangyou; CHEN Yonghe; LIU Xingpeng; LI Qi; LI Yue; LIU Yingbo; YIN Yihui; ZHAO Hao; ZHANG Wei; LI Haiou; JIN Zhi

doi:10.1049/cje.2021.07.024

Volume 30 Issue 6

Nov. 2021

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Article Navigation > Chinese Journal of Electronics > 2021 > 30(6): 1017-1021

WANG Bo, DING Peng, FENG Ruize, WANG Yanfu, LIU Xiaoyu, SUN Tangyou, CHEN Yonghe, LIU Xingpeng, LI Qi, LI Yue, LIU Yingbo, YIN Yihui, ZHAO Hao, ZHANG Wei, LI Haiou, JIN Zhi. Ultra-thin Body Buried In0.35Ga0.65As Channel MOSFETs with Extremely Low Off-current on Si Substrates[J]. Chinese Journal of Electronics, 2021, 30(6): 1017-1021. doi: 10.1049/cje.2021.07.024

Citation:

WANG Bo, DING Peng, FENG Ruize, WANG Yanfu, LIU Xiaoyu, SUN Tangyou, CHEN Yonghe, LIU Xingpeng, LI Qi, LI Yue, LIU Yingbo, YIN Yihui, ZHAO Hao, ZHANG Wei, LI Haiou, JIN Zhi. Ultra-thin Body Buried In_0.35Ga_0.65As Channel MOSFETs with Extremely Low Off-current on Si Substrates[J]. Chinese Journal of Electronics, 2021, 30(6): 1017-1021. doi: 10.1049/cje.2021.07.024

Citation:

WANG Bo, DING Peng, FENG Ruize, WANG Yanfu, LIU Xiaoyu, SUN Tangyou, CHEN Yonghe, LIU Xingpeng, LI Qi, LI Yue, LIU Yingbo, YIN Yihui, ZHAO Hao, ZHANG Wei, LI Haiou, JIN Zhi. Ultra-thin Body Buried In_0.35Ga_0.65As Channel MOSFETs with Extremely Low Off-current on Si Substrates[J]. Chinese Journal of Electronics, 2021, 30(6): 1017-1021. doi: 10.1049/cje.2021.07.024

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Ultra-thin Body Buried In_0.35Ga_0.65As Channel MOSFETs with Extremely Low Off-current on Si Substrates

doi: 10.1049/cje.2021.07.024

1. Guangxi Key Laboratory of Precision Navigation Technology and Application, Guilin University of Electronic Technology, Guilin 541004, China;
2. High-Frequency High-Voltage Device and Integrated Circuits Center, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China;
3. The 34th Research Institute of China Electronics Technology Group Corporation, Guilin 541004, China;
4. State Key Laboratory of ASIC & System, Fudan University, Shanghai 200433, China

Funds:

This work is supported by the National Natural Science Foundation of China (No.61874036, No.61805053), the Open Project of State Key Laboratory of ASIC and System (No.KVH1233021), the Guangxi Innovation Research Team Project (No.2018GXNSFGA281004, No.2018GXNSFBA281152), the Guangxi Innovation Driven Development Special Fund Project (No.AA19254015), and the Guangxi Key Laboratory of Precision Navigation Technology and Application Project (No.DH202020, No.DH202001).

Received Date: 2020-10-28
Rev Recd Date: 2021-01-11

Available Online: 2021-09-23

Publish Date: 2021-11-05

Abstract

Abstract

In this paper, we investigated the electrical properties of the Metal-oxide-semiconductor gate stack of Ti/Al₂O₃/InP under different annealing conditions. A minimum interface trap density of 3×10¹¹cm^-2eV^-1 is obtained without postmetallization annealing treatment. Additionally, utilizing Ti/Al₂O₃/InP MOS gate stack, we fabricated ultra-thin body buried In_0.35Ga_0.65As channel MOSFETs on Si substrates with optimized on/off trade-off. The 200nm gate length device with extremely low off-current of 0.6nA/µm, and on-off ratio of 3.3×10⁵, is demonstrated by employing buried low indium (In_0.35Ga_0.65As) channel with InP barrier/spacer device structure, giving strong potential for future highperformance and low-power applications.
- Buried low indium channel,
- Si substrate,
- Wafer bonding,
- Off-current

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References(17)

References

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