Volume 30 Issue 6
Nov.  2021
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WANG Bo, DING Peng, FENG Ruize, WANG Yanfu, LIU Xiaoyu, SUN Tangyou, CHEN Yonghe, LIU Xingpeng, LI Qi, LI Yue, LIU Yingbo, YIN Yihui, ZHAO Hao, ZHANG Wei, LI Haiou, JIN Zhi. Ultra-thin Body Buried In0.35Ga0.65As Channel MOSFETs with Extremely Low Off-current on Si Substrates[J]. Chinese Journal of Electronics, 2021, 30(6): 1017-1021. doi: 10.1049/cje.2021.07.024
Citation: WANG Bo, DING Peng, FENG Ruize, WANG Yanfu, LIU Xiaoyu, SUN Tangyou, CHEN Yonghe, LIU Xingpeng, LI Qi, LI Yue, LIU Yingbo, YIN Yihui, ZHAO Hao, ZHANG Wei, LI Haiou, JIN Zhi. Ultra-thin Body Buried In0.35Ga0.65As Channel MOSFETs with Extremely Low Off-current on Si Substrates[J]. Chinese Journal of Electronics, 2021, 30(6): 1017-1021. doi: 10.1049/cje.2021.07.024

Ultra-thin Body Buried In0.35Ga0.65As Channel MOSFETs with Extremely Low Off-current on Si Substrates

doi: 10.1049/cje.2021.07.024
Funds:

This work is supported by the National Natural Science Foundation of China (No.61874036, No.61805053), the Open Project of State Key Laboratory of ASIC and System (No.KVH1233021), the Guangxi Innovation Research Team Project (No.2018GXNSFGA281004, No.2018GXNSFBA281152), the Guangxi Innovation Driven Development Special Fund Project (No.AA19254015), and the Guangxi Key Laboratory of Precision Navigation Technology and Application Project (No.DH202020, No.DH202001).

  • Received Date: 2020-10-28
  • Rev Recd Date: 2021-01-11
  • Available Online: 2021-09-23
  • Publish Date: 2021-11-05
  • In this paper, we investigated the electrical properties of the Metal-oxide-semiconductor gate stack of Ti/Al2O3/InP under different annealing conditions. A minimum interface trap density of 3×1011cm-2eV-1 is obtained without postmetallization annealing treatment. Additionally, utilizing Ti/Al2O3/InP MOS gate stack, we fabricated ultra-thin body buried In0.35Ga0.65As channel MOSFETs on Si substrates with optimized on/off trade-off. The 200nm gate length device with extremely low off-current of 0.6nA/µm, and on-off ratio of 3.3×105, is demonstrated by employing buried low indium (In0.35Ga0.65As) channel with InP barrier/spacer device structure, giving strong potential for future highperformance and low-power applications.
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