A Design of 2-Stage Voltage Ramp-Up SRAM Physical Unclonable Function

Silicon physical unclonable function (PUF) implemented by static random access memory (SRAM) exists inherent demerit of unstable cells due to noise of environment and circuits, which significantly restricts its reproducibility. In this paper, a 16T SRAM cell with reset-delay circuit and a 2-stage voltage ramp up is fabricated and reported. Compared to conventional SRAM structure, each PUF cell adds a pair of pull-up PMOS (P-channel metal oxide semiconductor) and pull-down NMOS (N-channel metal oxide semiconductor) controlled by reset and delayed-reset signals respectively, resulting in two positive feedback stages with different amplification coefficients when the voltage is ramped up. PUF array consists of 4064 cells, 322 dummy cells and a group of 8 series-connected inverters with an area of 304 μm × 650 μm to match the digital post-processing module. PUF test chip was fabricated in HHGrace 110 nm platform with total area 1140 × 1140 μm². The average HDintra (intra-chip Hamming distance, also bit error rate, BER) and HDinter (inter-chip Hamming distance) values of the 50 PUF chips in SOP16 package measured at normal point (1.5 V/25 ℃) were 1.92% and 49.85%, respectively.